diff mbox series

[PULL,84/85] hw/hppa: Turn on 64-bit CPU for C3700 machine

Message ID	20231107030407.8979-85-richard.henderson@linaro.org
State	Accepted
Commit	fd9b04bf9299e8db36db3b677bc0a433fc3a34b3
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: Helge Deller <deller@gmx.de> Subject: [PULL 84/85] hw/hppa: Turn on 64-bit CPU for C3700 machine Date: Mon, 6 Nov 2023 19:04:06 -0800 Message-Id: <20231107030407.8979-85-richard.henderson@linaro.org> In-Reply-To: <20231107030407.8979-1-richard.henderson@linaro.org> References: <20231107030407.8979-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/85] target/hppa: Include PSW_P in tb flags and mmu index \| expand [PULL,01/85] target/hppa: Include PSW_P in tb flags and mmu index [PULL,02/85] target/hppa: Rename hppa_tlb_entry to HPPATLBEntry [PULL,03/85] target/hppa: Use IntervalTreeNode in HPPATLBEntry [PULL,04/85] target/hppa: Always report one page to tlb_set_page [PULL,05/85] target/hppa: Split out hppa_flush_tlb_range [PULL,06/85] target/hppa: Populate an interval tree with valid tlb entries [PULL,07/85] target/hppa: Remove get_temp [PULL,08/85] target/hppa: Remove get_temp_tl [PULL,09/85] target/hppa: Remove load_const [PULL,10/85] target/hppa: Fix hppa64 case in machine.c [PULL,11/85] target/hppa: Fix load in do_load_32 [PULL,12/85] target/hppa: Truncate rotate count in trans_shrpw_sar [PULL,13/85] target/hppa: Fix trans_ds for hppa64 [PULL,14/85] target/hppa: Fix do_add, do_sub for hppa64 [PULL,15/85] target/hppa: Fix bb_sar for hppa64 [PULL,16/85] target/hppa: Fix extrw and depw with sar for hppa64 [PULL,17/85] target/hppa: Introduce TYPE_HPPA64_CPU [PULL,18/85] target/hppa: Make HPPA_BTLB_ENTRIES variable [PULL,19/85] target/hppa: Implement cpu_list [PULL,20/85] target/hppa: Implement hppa_cpu_class_by_name [PULL,21/85] target/hppa: Update cpu_hppa_get/put_psw for hppa64 [PULL,22/85] target/hppa: Handle absolute addresses for pa2.0 [PULL,23/85] target/hppa: Adjust hppa_cpu_dump_state for hppa64 [PULL,24/85] target/hppa: Fix hppa64 addressing [PULL,25/85] target/hppa: Pass DisasContext to copy_iaoq_entry [PULL,26/85] target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb] [PULL,27/85] target/hppa: Use copy_iaoq_entry for link in do_ibranch [PULL,28/85] target/hppa: Mask inputs in copy_iaoq_entry [PULL,29/85] target/hppa: sar register allows only 5 bits on 32-bit CPU [PULL,30/85] target/hppa: Pass d to do_cond [PULL,31/85] target/hppa: Pass d to do_sub_cond [PULL,32/85] target/hppa: Pass d to do_log_cond [PULL,33/85] target/hppa: Pass d to do_sed_cond [PULL,34/85] target/hppa: Pass d to do_unit_cond [PULL,35/85] linux-user/hppa: Fixes for TARGET_ABI32 [PULL,36/85] target/hppa: Drop attempted gdbstub support for hppa64 [PULL,37/85] target/hppa: Remove TARGET_HPPA64 [PULL,38/85] target/hppa: Decode d for logical instructions [PULL,39/85] target/hppa: Decode d for unit instructions [PULL,40/85] target/hppa: Decode d for cmpclr instructions [PULL,41/85] target/hppa: Decode d for add instructions [PULL,42/85] target/hppa: Decode d for sub instructions [PULL,43/85] target/hppa: Decode d for bb instructions [PULL,44/85] target/hppa: Decode d for cmpb instructions [PULL,45/85] target/hppa: Decode CMPIB double-word [PULL,46/85] target/hppa: Decode ADDB double-word [PULL,47/85] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA [PULL,48/85] target/hppa: Implement DEPD, DEPDI [PULL,49/85] target/hppa: Implement EXTRD [PULL,50/85] target/hppa: Implement SHRPD [PULL,51/85] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM [PULL,52/85] target/hppa: Implement STDBY [PULL,53/85] target/hppa: Implement IDTLBT, IITLBT [PULL,54/85] hw/hppa: Use uint32_t instead of target_ureg [PULL,55/85] target/hppa: Remove TARGET_REGISTER_BITS [PULL,56/85] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections [PULL,57/85] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections [PULL,58/85] target/hppa: Adjust vmstate_env for pa2.0 tlb [PULL,59/85] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new [PULL,60/85] target/hppa: Replace tcg_gen__tl with tcg_gen__i64 [PULL,61/85] target/hppa: Implement HADD [PULL,62/85] target/hppa: Implement HSUB [PULL,63/85] target/hppa: Implement HAVG [PULL,64/85] target/hppa: Implement HSHL, HSHR [PULL,65/85] target/hppa: Implement HSHLADD, HSHRADD [PULL,66/85] target/hppa: Implement MIXH, MIXW [PULL,67/85] target/hppa: Implement PERMH [PULL,68/85] target/hppa: Fix interruption based on default PSW [PULL,69/85] target/hppa: Precompute zero into DisasContext [PULL,70/85] target/hppa: Return zero for r0 from load_gpr [PULL,71/85] include/hw/elf: Remove truncating signed casts [PULL,72/85] hw/hppa: Translate phys addresses for the cpu [PULL,73/85] linux-user/hppa: Drop EXCP_DUMP from handled exceptions [PULL,74/85] target/hppa: Implement pa2.0 data prefetch instructions [PULL,75/85] target/hppa: Add pa2.0 cpu local tlb flushes [PULL,76/85] target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system [PULL,77/85] target/hppa: Clear upper bits in mtctl for pa1.x [PULL,78/85] target/hppa: Add unwind_breg to CPUHPPAState [PULL,79/85] target/hppa: Create raise_exception_with_ior [PULL,80/85] target/hppa: Update IIAOQ, IIASQ for pa2.0 [PULL,81/85] target/hppa: Improve interrupt logging [PULL,82/85] hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region [PULL,83/85] hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory [PULL,84/85] hw/hppa: Turn on 64-bit CPU for C3700 machine [PULL,85/85] hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only

Commit Message

Richard Henderson Nov. 7, 2023, 3:04 a.m. UTC

From: Helge Deller <deller@gmx.de>

Signed-off-by: Helge Deller <deller@gmx.de>
---
 hw/hppa/machine.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 43c7afb89d..da9ca85806 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -696,7 +696,7 @@  static void HP_C3700_machine_init_class_init(ObjectClass *oc, void *data)
     NMIClass *nc = NMI_CLASS(oc);
 
     mc->desc = "HP C3700 workstation";
-    mc->default_cpu_type = TYPE_HPPA_CPU;
+    mc->default_cpu_type = TYPE_HPPA64_CPU;
     mc->init = machine_HP_C3700_init;
     mc->reset = hppa_machine_reset;
     mc->block_default_type = IF_SCSI;