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[176.184.46.187]) by smtp.gmail.com with ESMTPSA id p17-20020a5d48d1000000b003316ad360c1sm692737wrs.24.2023.11.16.23.17.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 16 Nov 2023 23:17:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Subbaraya Sundeep , Arnaud Minier , Igor Mammedov , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Tyrone Ting , Hao Wu , Marcel Apfelbaum , Felipe Balbi , qemu-arm@nongnu.org, =?utf-8?q?In=C3=A8s_V?= =?utf-8?q?arhol?= , Alistair Francis , Yanan Wang , Richard Henderson , Eduardo Habkost , Peter Maydell , Helge Deller , Subbaraya Sundeep , Alexandre Iooss , Gavin Shan Subject: [PATCH-for-8.2? v2 2/4] hw/arm/stm32f405: Report error when incorrect CPU is used Date: Fri, 17 Nov 2023 08:17:02 +0100 Message-ID: <20231117071704.35040-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231117071704.35040-1-philmd@linaro.org> References: <20231117071704.35040-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M4 CPU: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu The valid types are: cortex-m4-arm-cpu Since the SoC family can only use Cortex-M4 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gavin Shan Reviewed-by: Alistair Francis --- include/hw/arm/stm32f405_soc.h | 4 ---- hw/arm/netduinoplus2.c | 7 ++++++- hw/arm/olimex-stm32-h405.c | 8 ++++++-- hw/arm/stm32f405_soc.c | 8 +------- 4 files changed, 13 insertions(+), 14 deletions(-) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index c968ce3ab2..d15c03c4b5 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) #define CCM_SIZE (64 * 1024) struct STM32F405State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; ARMv7MState armv7m; diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 515c081605..2e58984947 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine) static void netduinoplus2_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; mc->init = netduinoplus2_init; + mc->valid_cpu_types = valid_cpu_types; } DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 3aa61c91b7..d793de7c97 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine) static void olimex_stm32_h405_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc = "Olimex STM32-H405 (Cortex-M4)"; mc->init = olimex_stm32_h405_init; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); + mc->valid_cpu_types = valid_cpu_types; /* SRAM pre-allocated as part of the SoC instantiation */ mc->default_ram_size = 0; diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index cef23d7ee4..a65bbe298d 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) create_unimplemented_device("RNG", 0x50060800, 0x400); } -static Property stm32f405_soc_properties[] = { - DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f405_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = stm32f405_soc_realize; - device_class_set_props(dc, stm32f405_soc_properties); /* No vmstate or reset required: device has no internal state */ }