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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 10/33] hw/cpu/arm: Introduce abstract CORTEX_MPCORE_PRIV QOM type Date: Tue, 12 Dec 2023 17:29:10 +0100 Message-ID: <20231212162935.42910-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This type will be common to A9MPCORE/A15MPCORE devices. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater --- include/hw/cpu/cortex_mpcore.h | 21 +++++++++++++++++++++ hw/cpu/cortex_mpcore.c | 22 ++++++++++++++++++++++ hw/arm/Kconfig | 3 +++ hw/cpu/meson.build | 1 + 4 files changed, 47 insertions(+) create mode 100644 hw/cpu/cortex_mpcore.c diff --git a/include/hw/cpu/cortex_mpcore.h b/include/hw/cpu/cortex_mpcore.h index 9147f35c2a..c5dd7200d0 100644 --- a/include/hw/cpu/cortex_mpcore.h +++ b/include/hw/cpu/cortex_mpcore.h @@ -17,6 +17,27 @@ #include "hw/timer/a9gtimer.h" #include "hw/timer/arm_mptimer.h" +/* + * This is a model of the Arm Cortex-A MPCore family of hardware. + * + * The A7 and A15 MPCore contain: + * up to 4 Cortex-A cores + * a GIC + * The A9 MPCore additionally contains: + * a System Control Unit + * some timers and watchdogs + */ +#define TYPE_CORTEX_MPCORE_PRIV "cortex_mpcore_priv" +OBJECT_DECLARE_TYPE(CortexMPPrivState, CortexMPPrivClass, CORTEX_MPCORE_PRIV) + +struct CortexMPPrivClass { + SysBusDeviceClass parent_class; +}; + +struct CortexMPPrivState { + SysBusDevice parent_obj; +}; + #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" OBJECT_DECLARE_SIMPLE_TYPE(A9MPPrivState, A9MPCORE_PRIV) diff --git a/hw/cpu/cortex_mpcore.c b/hw/cpu/cortex_mpcore.c new file mode 100644 index 0000000000..7d3796bd69 --- /dev/null +++ b/hw/cpu/cortex_mpcore.c @@ -0,0 +1,22 @@ +/* + * Cortex-MPCore internal peripheral emulation. + * + * Copyright (c) 2023 Linaro Limited. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/cpu/cortex_mpcore.h" + +static const TypeInfo cortex_mpcore_types[] = { + { + .name = TYPE_CORTEX_MPCORE_PRIV, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(CortexMPPrivState), + .class_size = sizeof(CortexMPPrivClass), + .abstract = true, + }, +}; + +DEFINE_TYPES(cortex_mpcore_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3ada335a24..3040342fcb 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -643,6 +643,9 @@ config ZAURUS select NAND select ECC +config CORTEX_MPCORE + bool + config A9MPCORE bool select A9_GTIMER diff --git a/hw/cpu/meson.build b/hw/cpu/meson.build index 6d319947ca..8b376d6e7c 100644 --- a/hw/cpu/meson.build +++ b/hw/cpu/meson.build @@ -2,5 +2,6 @@ system_ss.add(files('core.c', 'cluster.c')) system_ss.add(when: 'CONFIG_ARM11MPCORE', if_true: files('arm11mpcore.c')) system_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview_mpcore.c')) +specific_ss.add(when: 'CONFIG_CORTEX_MPCORE', if_true: files('cortex_mpcore.c')) specific_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c')) specific_ss.add(when: 'CONFIG_A15MPCORE', if_true: files('a15mpcore.c'))