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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 15/33] hw/cpu/arm: Handle 'gic-irq' property once in MPCore parent Date: Tue, 12 Dec 2023 17:29:15 +0100 Message-ID: <20231212162935.42910-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move the 'num-irq' property to the abstract QOM parent. Rename it as 'gic-irq', keeping it aliased as 'num-irq'. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/cpu/cortex_mpcore.h | 13 +++++++++---- hw/cpu/a15mpcore.c | 28 +++++++++++++--------------- hw/cpu/a9mpcore.c | 28 +++++++++++++--------------- hw/cpu/cortex_mpcore.c | 5 +++++ 4 files changed, 40 insertions(+), 34 deletions(-) diff --git a/include/hw/cpu/cortex_mpcore.h b/include/hw/cpu/cortex_mpcore.h index 387552468c..96da713be9 100644 --- a/include/hw/cpu/cortex_mpcore.h +++ b/include/hw/cpu/cortex_mpcore.h @@ -32,6 +32,8 @@ * the cluster. * + QOM properties "cpu-has-el3", "cpu-has-el2" which set whether the CPUs * have the exception level features present. + * + QOM property "gic-spi-num" sets the number of GIC Shared Peripheral + * Interrupts. */ #define TYPE_CORTEX_MPCORE_PRIV "cortex_mpcore_priv" OBJECT_DECLARE_TYPE(CortexMPPrivState, CortexMPPrivClass, CORTEX_MPCORE_PRIV) @@ -39,6 +41,8 @@ OBJECT_DECLARE_TYPE(CortexMPPrivState, CortexMPPrivClass, CORTEX_MPCORE_PRIV) /** * CortexMPPrivClass: * @container_size - size of the device's MMIO region + * @gic_spi_default - default number of GIC SPIs + * @gic_spi_max - maximum number of GIC SPIs */ struct CortexMPPrivClass { SysBusDeviceClass parent_class; @@ -46,6 +50,9 @@ struct CortexMPPrivClass { DeviceRealize parent_realize; uint64_t container_size; + + unsigned gic_spi_default; + unsigned gic_spi_max; }; struct CortexMPPrivState { @@ -58,6 +65,8 @@ struct CortexMPPrivState { bool cpu_has_el3; bool cpu_has_el2; + + uint32_t gic_spi_num; }; #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" @@ -66,8 +75,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(A9MPPrivState, A9MPCORE_PRIV) struct A9MPPrivState { CortexMPPrivState parent_obj; - uint32_t num_irq; - A9SCUState scu; GICState gic; A9GTimerState gtimer; @@ -81,8 +88,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(A15MPPrivState, A15MPCORE_PRIV) struct A15MPPrivState { CortexMPPrivState parent_obj; - uint32_t num_irq; - GICState gic; }; diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index a16544fdde..195355b589 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -61,7 +61,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", c->num_cores); - qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-irq", c->gic_spi_num); if (!kvm_irqchip_in_kernel()) { /* Make the GIC's TZ support match the CPUs. We assume that @@ -83,14 +83,14 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) sysbus_pass_irq(sbd, gicsbd); /* Pass through inbound GPIO lines to the GIC */ - qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32); + qdev_init_gpio_in(dev, a15mp_priv_set_irq, c->gic_spi_num - 32); /* Wire the outputs from each CPU's generic timer to the * appropriate GIC PPI inputs */ for (i = 0; i < c->num_cores; i++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); - int ppibase = s->num_irq - 32 + i * 32; + int ppibase = c->gic_spi_num - 32 + i * 32; int irq; /* Mapping from the output timer irq lines from the CPU to the * GIC PPI inputs used on the A15: @@ -142,17 +142,6 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) } } -static Property a15mp_priv_properties[] = { - /* The Cortex-A15MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 128+32, which - * is the number provided by the Cortex-A15MP test chip in the - * Versatile Express A15 development board. - * Other boards may differ and should set this property appropriately. - */ - DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), - DEFINE_PROP_END_OF_LIST(), -}; - static void a15mp_priv_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -160,9 +149,18 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data) cc->container_size = 0x8000; + /* + * The Cortex-A15MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 128+32, which + * is the number provided by the Cortex-A15MP test chip in the + * Versatile Express A15 development board. + * Other boards may differ and should set this property appropriately. + */ + cc->gic_spi_default = 160; + cc->gic_spi_max = 224; + device_class_set_parent_realize(dc, a15mp_priv_realize, &cc->parent_realize); - device_class_set_props(dc, a15mp_priv_properties); /* We currently have no saveable state */ } diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 54949314f8..72621bce64 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -78,7 +78,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", c->num_cores); - qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-irq", c->gic_spi_num); qdev_prop_set_uint32(gicdev, "num-priority-bits", A9_GIC_NUM_PRIORITY_BITS); @@ -96,7 +96,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) sysbus_pass_irq(sbd, gicbusdev); /* Pass through inbound GPIO lines to the GIC */ - qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); + qdev_init_gpio_in(dev, a9mp_priv_set_irq, c->gic_spi_num - 32); gtimerdev = DEVICE(&s->gtimer); qdev_prop_set_uint32(gtimerdev, "num-cpu", c->num_cores); @@ -150,7 +150,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) * timer is PPI 29 and the watchdog PPI 30. */ for (unsigned i = 0; i < c->num_cores; i++) { - int ppibase = (s->num_irq - 32) + i * 32; + int ppibase = (c->gic_spi_num - 32) + i * 32; sysbus_connect_irq(gtimerbusdev, i, qdev_get_gpio_in(gicdev, ppibase + 27)); sysbus_connect_irq(mptimerbusdev, i, @@ -160,17 +160,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) } } -static Property a9mp_priv_properties[] = { - /* The Cortex-A9MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 64+32, which - * is the number provided by the Cortex-A9MP test chip in the - * Realview PBX-A9 and Versatile Express A9 development boards. - * Other boards may differ and should set this property appropriately. - */ - DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), - DEFINE_PROP_END_OF_LIST(), -}; - static void a9mp_priv_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -178,8 +167,17 @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data) cc->container_size = 0x2000; + /* + * The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + * Other boards may differ and should set this property appropriately. + */ + cc->gic_spi_default = 96; + cc->gic_spi_max = 224; + device_class_set_parent_realize(dc, a9mp_priv_realize, &cc->parent_realize); - device_class_set_props(dc, a9mp_priv_properties); } static const TypeInfo a9mp_types[] = { diff --git a/hw/cpu/cortex_mpcore.c b/hw/cpu/cortex_mpcore.c index 549b81f708..dee40a7bf2 100644 --- a/hw/cpu/cortex_mpcore.c +++ b/hw/cpu/cortex_mpcore.c @@ -21,6 +21,8 @@ static void cortex_mpcore_priv_instance_init(Object *obj) memory_region_init(&s->container, obj, "mpcore-priv-container", k->container_size); sysbus_init_mmio(sbd, &s->container); + + s->gic_spi_num = k->gic_spi_default; } static Property cortex_mpcore_priv_properties[] = { @@ -30,6 +32,9 @@ static Property cortex_mpcore_priv_properties[] = { DEFINE_PROP_BOOL("cpu-has-el3", CortexMPPrivState, cpu_has_el3, true), DEFINE_PROP_BOOL("cpu-has-el2", CortexMPPrivState, cpu_has_el2, false), + DEFINE_PROP_UINT32("gic-spi-num", CortexMPPrivState, gic_spi_num, 0), + DEFINE_PROP_UINT32("num-irq", CortexMPPrivState, gic_spi_num, 0), /* alias */ + DEFINE_PROP_END_OF_LIST(), };