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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 21/33] hw/cpu/arm: Create CPUs once in MPCore parent Date: Tue, 12 Dec 2023 17:29:21 +0100 Message-ID: <20231212162935.42910-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add support for creating the MPCore CPU cluster in the abstract TYPE_CORTEX_MPCORE_PRIV parent realize() handler. Only do so if the 'cpu-type' property is set, so current behavior is not modified. Boards will be converted by setting this property. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/cpu/cortex_mpcore.h | 12 +++++ hw/cpu/cortex_mpcore.c | 88 ++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/include/hw/cpu/cortex_mpcore.h b/include/hw/cpu/cortex_mpcore.h index 4e1aa9f7f7..9a4fc2404e 100644 --- a/include/hw/cpu/cortex_mpcore.h +++ b/include/hw/cpu/cortex_mpcore.h @@ -16,6 +16,7 @@ #include "hw/misc/a9scu.h" #include "hw/timer/a9gtimer.h" #include "hw/timer/arm_mptimer.h" +#include "target/arm/cpu-qom.h" /* * This is a model of the Arm Cortex-A MPCore family of hardware. @@ -93,13 +94,24 @@ struct CortexMPPrivState { SysBusDevice parent_obj; MemoryRegion container; + ARMCPU *cpu[4]; GICState gic; /* Properties */ + uint8_t cluster_id; uint32_t num_cores; + char *cpu_type; bool cpu_has_el3; bool cpu_has_el2; + bool cpu_has_vfp_d32; + bool cpu_has_neon; + uint64_t cpu_freq_hz; + uint64_t cpu_midr; + uint32_t cpu_psci_conduit; + uint64_t cpu_reset_cbar; + bool cpu_reset_hivecs; + MemoryRegion *cpu_memory; uint32_t gic_spi_num; }; diff --git a/hw/cpu/cortex_mpcore.c b/hw/cpu/cortex_mpcore.c index 75324268fa..65309636d7 100644 --- a/hw/cpu/cortex_mpcore.c +++ b/hw/cpu/cortex_mpcore.c @@ -12,6 +12,7 @@ #include "hw/cpu/cortex_mpcore.h" #include "hw/irq.h" #include "sysemu/kvm.h" +#include "target/arm/cpu.h" static void cortex_mpcore_priv_set_irq(void *opaque, int irq, int level) { @@ -50,6 +51,12 @@ static void cortex_mpcore_priv_realize(DeviceState *dev, Error **errp) return; } + if (s->num_cores > ARRAY_SIZE(s->cpu)) { + error_setg(errp, + "At most %zu CPU cores are supported", ARRAY_SIZE(s->cpu)); + return; + } + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cores); qdev_prop_set_uint32(gicdev, "num-irq", s->gic_spi_num); if (k->gic_priority_bits) { @@ -75,14 +82,95 @@ static void cortex_mpcore_priv_realize(DeviceState *dev, Error **errp) /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(dev, cortex_mpcore_priv_set_irq, s->gic_spi_num - 32); + + + /* CPU */ + if (!s->cpu_type) { + return; + } + for (int i = 0; i < s->num_cores; i++) { + Object *cpuobj; + + cpuobj = object_new(s->cpu_type); + object_property_add_child(OBJECT(dev), "cpu[*]", OBJECT(cpuobj)); + object_unref(cpuobj); + s->cpu[i] = ARM_CPU(cpuobj); + + object_property_set_bool(cpuobj, "neon", s->cpu_has_neon, + &error_abort); + object_property_set_bool(cpuobj, "vfp-d32", s->cpu_has_vfp_d32, + &error_abort); + if (object_property_find(cpuobj, "has_el3")) { + object_property_set_bool(cpuobj, "has_el3", s->cpu_has_el3, + &error_abort); + } + if (object_property_find(cpuobj, "has_el2")) { + object_property_set_bool(cpuobj, "has_el2", s->cpu_has_el2, + &error_abort); + } + if (s->cpu_freq_hz) { + object_property_set_int(cpuobj, "cntfrq", s->cpu_freq_hz, + &error_abort); + } + object_property_set_int(cpuobj, "midr", s->cpu_midr, &error_abort); + object_property_set_bool(cpuobj, "reset-hivecs", s->cpu_reset_hivecs, + &error_abort); + if (s->num_cores == 1) { + /* On uniprocessor, the CBAR is set to 0 */ + } else if (object_property_find(cpuobj, "reset-cbar")) { + object_property_set_int(cpuobj, "reset-cbar", + s->cpu_reset_cbar, &error_abort); + } + if (i > 0) { + /* + * Secondary CPUs start in powered-down state (and can be + * powered up via the SRC system reset controller) + */ + object_property_set_bool(cpuobj, "start-powered-off", true, + &error_abort); + } + if (s->cluster_id) { + object_property_set_int(cpuobj, "mp-affinity", + (s->cluster_id << ARM_AFF1_SHIFT) | i, + &error_abort); + } else { + object_property_set_int(cpuobj, "mp-affinity", + arm_cpu_mp_affinity(i, s->num_cores), + &error_abort); + } + object_property_set_int(cpuobj, "psci-conduit", + s->cpu_psci_conduit, &error_abort); + if (s->cpu_memory) { + object_property_set_link(cpuobj, "memory", + OBJECT(s->cpu_memory), &error_abort); + } + + if (!qdev_realize(DEVICE(s->cpu[i]), NULL, errp)) { + return; + } + } } static Property cortex_mpcore_priv_properties[] = { + DEFINE_PROP_UINT8("cluster-id", CortexMPPrivState, cluster_id, 0), DEFINE_PROP_UINT32("num-cores", CortexMPPrivState, num_cores, 1), DEFINE_PROP_UINT32("num-cpu", CortexMPPrivState, num_cores, 1), /* alias */ + DEFINE_PROP_STRING("cpu-type", CortexMPPrivState, cpu_type), DEFINE_PROP_BOOL("cpu-has-el3", CortexMPPrivState, cpu_has_el3, true), DEFINE_PROP_BOOL("cpu-has-el2", CortexMPPrivState, cpu_has_el2, false), + DEFINE_PROP_BOOL("cpu-has-vfp-d32", CortexMPPrivState, cpu_has_vfp_d32, + true), + DEFINE_PROP_BOOL("cpu-has-neon", CortexMPPrivState, cpu_has_neon, true), + DEFINE_PROP_UINT64("cpu-freq-hz", CortexMPPrivState, cpu_freq_hz, 0), + DEFINE_PROP_UINT64("cpu-midr", CortexMPPrivState, cpu_midr, 0), + DEFINE_PROP_UINT32("cpu-psci-conduit", CortexMPPrivState, cpu_psci_conduit, + QEMU_PSCI_CONDUIT_DISABLED), + DEFINE_PROP_UINT64("cpu-reset-cbar", CortexMPPrivState, cpu_reset_cbar, 0), + DEFINE_PROP_BOOL("cpu-reset-hivecs", CortexMPPrivState, cpu_reset_hivecs, + false), + DEFINE_PROP_LINK("cpu-memory", CortexMPPrivState, cpu_memory, + TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("gic-spi-num", CortexMPPrivState, gic_spi_num, 0), DEFINE_PROP_UINT32("num-irq", CortexMPPrivState, gic_spi_num, 0), /* alias */