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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 25/33] hw/arm/fsl-imx6ul: Let the A7MPcore create/wire the CPU cores Date: Tue, 12 Dec 2023 17:29:25 +0100 Message-ID: <20231212162935.42910-26-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set the properties on the a7mpcore object to let it create and wire the CPU cores. Remove the redundant code. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/fsl-imx6ul.h | 4 ---- hw/arm/fsl-imx6ul.c | 24 ++++++------------------ hw/arm/mcimx6ul-evk.c | 3 ++- 3 files changed, 8 insertions(+), 23 deletions(-) diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index b37d544319..9957ab5be0 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -34,7 +34,6 @@ #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" #include "exec/memory.h" -#include "cpu.h" #include "qom/object.h" #include "qemu/units.h" @@ -63,11 +62,8 @@ enum FslIMX6ULConfiguration { }; struct FslIMX6ULState { - /*< private >*/ DeviceState parent_obj; - /*< public >*/ - ARMCPU cpu; CortexMPPrivState a7mpcore; IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS]; IMXEPITState epit[FSL_IMX6UL_NUM_EPITS]; diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 6e4343efaa..512973e3c1 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -25,6 +25,7 @@ #include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "target/arm/cpu.h" /* qom */ #define NAME_SIZE 20 @@ -34,9 +35,6 @@ static void fsl_imx6ul_init(Object *obj) char name[NAME_SIZE]; int i; - object_initialize_child(obj, "cpu0", &s->cpu, - ARM_CPU_TYPE_NAME("cortex-a7")); - /* * A7MPCORE */ @@ -158,8 +156,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) DeviceState *gic; int i; char name[NAME_SIZE]; - SysBusDevice *sbd; - DeviceState *d; if (ms->smp.cpus > 1) { error_setg(errp, "%s: Only a single CPU is supported (%d requested)", @@ -167,26 +163,18 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) return; } - qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); - /* * A7MPCORE */ - object_property_set_int(OBJECT(&s->a7mpcore), "num-cores", 1, &error_abort); - object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", - FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort); + qdev_prop_set_uint32(DEVICE(&s->a7mpcore), "num-cores", 1); + qdev_prop_set_string(DEVICE(&s->a7mpcore), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-a7")); + qdev_prop_set_uint32(DEVICE(&s->a7mpcore), "gic-spi-num", + FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL); sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); gic = DEVICE(&s->a7mpcore); - sbd = SYS_BUS_DEVICE(&s->a7mpcore); - d = DEVICE(&s->cpu); - - sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); - sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); - sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ)); - sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ)); - /* * A7MPCORE DAP */ diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 500427e94b..a19834930f 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -18,6 +18,7 @@ #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" +#include "target/arm/cpu.h" /* qom */ static void mcimx6ul_evk_init(MachineState *machine) { @@ -64,7 +65,7 @@ static void mcimx6ul_evk_init(MachineState *machine) } if (!qtest_enabled()) { - arm_load_kernel(&s->cpu, machine, &boot_info); + arm_load_kernel(s->a7mpcore.cpu[0], machine, &boot_info); } }