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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id t26-20020adfa2da000000b00337c0cacf54sm7579061wra.101.2024.01.19.15.23.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 15:23:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , David Hildenbrand , Thomas Huth , qemu-s390x@nongnu.org, Ilya Leoshkevich , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 15/38 3/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (3/5) Date: Sat, 20 Jan 2024 00:22:59 +0100 Message-ID: <20240119232302.50393-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240110224408.10444-16-richard.henderson@linaro.org> References: <20240110224408.10444-16-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Code movement to ease review, no logical change. Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/tcg/translate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index aedce85029..fd1138c684 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -910,12 +910,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) cond = TCG_COND_NE; c->u.s32.b = tcg_constant_i32(1); break; - case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */ - cond = TCG_COND_EQ; - c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_constant_i32(0); - tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); - break; case 0x8 | 0x4: /* cc < 2 */ cond = TCG_COND_LTU; c->u.s32.b = tcg_constant_i32(2); @@ -924,6 +918,18 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) cond = TCG_COND_EQ; c->u.s32.b = tcg_constant_i32(0); break; + case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */ + cond = TCG_COND_NE; + c->u.s32.a = tcg_temp_new_i32(); + c->u.s32.b = tcg_constant_i32(0); + tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); + break; + case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */ + cond = TCG_COND_EQ; + c->u.s32.a = tcg_temp_new_i32(); + c->u.s32.b = tcg_constant_i32(0); + tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); + break; case 0x4 | 0x2 | 0x1: /* cc != 0 */ cond = TCG_COND_NE; c->u.s32.b = tcg_constant_i32(0); @@ -932,12 +938,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) cond = TCG_COND_GTU; c->u.s32.b = tcg_constant_i32(1); break; - case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */ - cond = TCG_COND_NE; - c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_constant_i32(0); - tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); - break; default: /* CC is masked by something else: (8 >> cc) & mask. */ cond = TCG_COND_NE;