From patchwork Mon Jan 22 14:55:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 764642 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:10c4:b0:337:62d3:c6d5 with SMTP id b4csp1140371wrx; Mon, 22 Jan 2024 06:57:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IGzHL3tS8XCNw5JH8Ytn9HtYdSqad9PVXFRSTvKWEFGtwcpU1XqiZZsPiv2EDHNf1Hytm34 X-Received: by 2002:a05:6214:5098:b0:686:2bb0:bf2e with SMTP id kk24-20020a056214509800b006862bb0bf2emr3962426qvb.100.1705935427960; Mon, 22 Jan 2024 06:57:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705935427; cv=none; d=google.com; s=arc-20160816; b=sSEAN3RFTj07S/MEQs3bkHh2HqyiBLvC5Wl7BQsjzvseqUaUKnK3erKebgBgrlTTIK DbP7d+1bplMA8rE/YDTVcdrLt1XINApU3lhrsuLjIQsJTi13qfF7X6oPrH/4AYLzXKTi jCcMccJnnK6XdBW2cbpAv/AJTraBX/hEnwSoejMmY6RZITR074tBSsWFCLBtP4kOpoTW Gas/KBoXjwqoJI7IJ4lhHeGbfcOSgpXgTQAJuWBuyFGgYi8kAPdcxwEX0/W2aQDfNa2k QE8MXFnxJj+zWnv+ngF69Q4Bu2gRzrYlZNAsZIteFF8937IiUfEMdwcFxsrULxRpQz++ WDvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=sMNaDAt2JCjIWxO3MmU6Jb8mcwK8LOwQChx2t1zdH94=; fh=mGQIuaf4A7RZOxcauYqguCwKMqzWt70hd4nAkQm0M6A=; b=pAKgUIRMjqFZsjV16g8Wbv/Ae6X/sJ+iUKX1+xlMsuNrRQNJsIiSqIeRyFZUzJMH9Y utlAt/Dikm5dA/wHndsAtjZYY18dnOpeYl328J/kEVO+EzFLZKd/k8s+4GFy1/w+utj5 z5+S8hJI+arTm+AUE41W19LoNK/TLKSJ98tmBZAXg41xVpxqFrrPlGS2rNf6CLNiQMgQ Q7UgqlhBtN0sW5E3KpZqR9UGpGLOC8YubgDxbDnXzeAPdFJCN65XzQaHC+5ROzo1NpEw RhcCXyW4yt58WVNnfmDZ/B6dAL/ouNqr+CtpC4nPcOaTMkzX9g8dUP3Jfuls19FWl+dK hzDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EM8JSDJL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d4-20020a0cdb04000000b006819598b8eesi5823255qvk.211.2024.01.22.06.57.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2024 06:57:07 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EM8JSDJL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rRvis-00072j-TF; Mon, 22 Jan 2024 09:56:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rRvip-0006zi-07 for qemu-devel@nongnu.org; Mon, 22 Jan 2024 09:56:23 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rRvii-0008IG-4i for qemu-devel@nongnu.org; Mon, 22 Jan 2024 09:56:22 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-40e8801221cso32627365e9.1 for ; Mon, 22 Jan 2024 06:56:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705935374; x=1706540174; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sMNaDAt2JCjIWxO3MmU6Jb8mcwK8LOwQChx2t1zdH94=; b=EM8JSDJL0XTOqmMRPVvjBeyNJG/q01jf8OocmxkXxkBgRobo3cKNYi7/FpsoEjQT9K //BWH+fODFcF1o8eUU1iYm+97g5TSOao33ZLSziDZevlwszfqRoOS93JJINlIlW6Vk7W kimDp3S8oUJM7MDuMtgcXDbBuW/pss1/oG0pEezqIHSmNOVNmikS1Lrig4kT3a10r8MU P9GJu5Emqfpv7hXYa9MKcLj8+mY4j3EFjEgBLNEtUurI0iNFSiuj442UmSVABSN4KI43 cY2g1ofwdIEzQ8v7ew8WmWCVAGkN1bLWB1kB5k2rMsqyMH02nSYefm6XmGLGMaF7W/yD kOng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705935374; x=1706540174; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sMNaDAt2JCjIWxO3MmU6Jb8mcwK8LOwQChx2t1zdH94=; b=g7HblkmNEhLwcnvaMR91lVn/o/l0Fei4+TwNL8Kv2WLlBR19WvpvKVdmSAHoAgC94W BaIB+HAl2r6nlxvufYrveYRR1ba9+HbnuXuBnyd5U2+XkOzlxFdVK/TLrVLBX1iR/dlH p6FYqVGYXAWPSN+NtYduvdV+/xeN2YaCw8jCl8R575ZB+e9kWI2cAuix75K/WKwt0DSr BYUX/Q+tb953Jd41eOngnaTMtmC5oJ0IRdwlMA9DtAdBevStJlXnSiLTH5Kx1bpjJrvf ORXdmWBQSPUkI2F55ujGEdqi3sznNHLAMo7fB2pWiY00mHygPtdiaWklojUyahF0r4RN 41Zw== X-Gm-Message-State: AOJu0Yyc8Z6dOoSdAEAQBMT3ugTeleLf640o0ze9L0kdr7yMM06Iy4gg 6YfFhwSVa/MCKHKbSU5eBx+vvW+Yfxow/ZZR4HBshjOhjs0N2XhZce9gZQ073OY= X-Received: by 2002:a05:600c:3b96:b0:40e:70c0:5054 with SMTP id n22-20020a05600c3b9600b0040e70c05054mr3229863wms.2.1705935374582; Mon, 22 Jan 2024 06:56:14 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id f6-20020a05600c154600b0040e880ac6ecsm19550208wmg.35.2024.01.22.06.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 06:56:11 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 339205F8FC; Mon, 22 Jan 2024 14:56:11 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Marcel Apfelbaum , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Laurent Vivier , kvm@vger.kernel.org, Yoshinori Sato , Pierrick Bouvier , Palmer Dabbelt , Liu Zhiwei , Laurent Vivier , Yanan Wang , qemu-ppc@nongnu.org, Weiwei Li , qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , Peter Maydell , Alexandre Iooss , John Snow , Mahmoud Mandour , Wainer dos Santos Moschetta , Richard Henderson , Ilya Leoshkevich , Alistair Francis , David Woodhouse , Cleber Rosa , Beraldo Leal , Bin Meng , Nicholas Piggin , Aurelien Jarno , Daniel Henrique Barboza , Daniel Henrique Barboza , Thomas Huth , David Hildenbrand , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Paolo Bonzini , Song Gao , Eduardo Habkost , Brian Cain , Paul Durrant , Akihiko Odaki Subject: [PATCH v3 04/21] target/riscv: Validate misa_mxl_max only once Date: Mon, 22 Jan 2024 14:55:53 +0000 Message-Id: <20240122145610.413836-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240122145610.413836-1-alex.bennee@linaro.org> References: <20240122145610.413836-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki Message-Id: <20240103173349.398526-26-alex.bennee@linaro.org> Message-Id: <20231213-riscv-v7-4-a760156a337f@daynix.com> Signed-off-by: Alex Bennée Acked-by: Alistair Francis --- target/riscv/cpu.c | 21 +++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 23 ----------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dcc09a10875..7ee4f8520f9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1292,6 +1292,26 @@ static const MISAExtInfo misa_ext_info_arr[] = { MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), }; +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) +{ + CPUClass *cc = CPU_CLASS(mcc); + + /* Validate that MISA_MXL is set properly. */ + switch (mcc->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } +} + static int riscv_validate_misa_info_idx(uint32_t bit) { int idx; @@ -1833,6 +1853,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); mcc->misa_mxl_max = (uint32_t)(uintptr_t)data; + riscv_cpu_validate_misa_mxl(mcc); } static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 30f0a22a481..1cd659d992e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -268,27 +268,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) -{ - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc = CPU_CLASS(mcc); - - /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } -} - static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) { CPURISCVState *env = &cpu->env; @@ -935,8 +914,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) return false; } - riscv_cpu_validate_misa_mxl(cpu); - #ifndef CONFIG_USER_ONLY CPURISCVState *env = &cpu->env; Error *local_err = NULL;