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envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since previous commit the MIPSITUState::cpu0 field is not used anymore. Remove it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/misc/mips_itu.h | 1 - hw/mips/cps.c | 2 -- hw/misc/mips_itu.c | 5 ----- 3 files changed, 8 deletions(-) diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 3a7330ac07..de7400c1fe 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -73,7 +73,6 @@ struct MIPSITUState { /* SAAR */ uint64_t *saar; - ArchCPU *cpu0; }; /* Get ITC Configuration Tag memory region. */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 988ceaa0b9..07b73b0a1f 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -103,8 +103,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); - object_property_set_link(OBJECT(&s->itu), "cpu[0]", - OBJECT(first_cpu), &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index d259a88d22..9705efeafe 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -527,10 +527,6 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) s->num_semaphores); return; } - if (!s->cpu0) { - error_setg(errp, "Missing 'cpu[0]' property"); - return; - } s->cell = g_new(ITCStorageCell, get_num_cells(s)); } @@ -558,7 +554,6 @@ static Property mips_itu_properties[] = { ITC_FIFO_NUM_MAX), DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), - DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU *), DEFINE_PROP_END_OF_LIST(), };