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Wed, 13 Mar 2024 14:34:42 -0700 (PDT) Received: from m1x-phil.lan ([176.176.182.179]) by smtp.gmail.com with ESMTPSA id bk1-20020a0560001d8100b0033e95794186sm57071wrb.83.2024.03.13.14.34.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Mar 2024 14:34:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Paolo Bonzini , Thomas Huth , qemu-ppc@nongnu.org Subject: [PATCH-for-9.1 09/12] accel/tcg/internal: Check for USER_ONLY definition instead of SOFTMMU Date: Wed, 13 Mar 2024 22:33:36 +0100 Message-ID: <20240313213339.82071-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240313213339.82071-1-philmd@linaro.org> References: <20240313213339.82071-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/internal-target.h | 6 +++--- accel/tcg/tb-hash.h | 4 ++-- accel/tcg/tcg-all.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 4e36cf858e..b22b29c461 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -24,7 +24,7 @@ #define assert_memory_lock() #endif -#if defined(CONFIG_SOFTMMU) && defined(CONFIG_DEBUG_TCG) +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_DEBUG_TCG) void assert_no_pages_locked(void); #else static inline void assert_no_pages_locked(void) { } @@ -62,12 +62,12 @@ void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t); void tb_unlock_pages(TranslationBlock *); #endif -#ifdef CONFIG_SOFTMMU +#ifndef CONFIG_USER_ONLY void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, unsigned size, uintptr_t retaddr); G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); -#endif /* CONFIG_SOFTMMU */ +#endif /* !CONFIG_USER_ONLY */ TranslationBlock *tb_gen_code(CPUState *cpu, vaddr pc, uint64_t cs_base, uint32_t flags, diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h index a0c61f25cd..45a484ce82 100644 --- a/accel/tcg/tb-hash.h +++ b/accel/tcg/tb-hash.h @@ -25,7 +25,7 @@ #include "qemu/xxhash.h" #include "tb-jmp-cache.h" -#ifdef CONFIG_SOFTMMU +#ifndef CONFIG_USER_ONLY /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for addresses on the same page. The top bits are the same. This allows @@ -58,7 +58,7 @@ static inline unsigned int tb_jmp_cache_hash_func(vaddr pc) return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1); } -#endif /* CONFIG_SOFTMMU */ +#endif /* CONFIG_USER_ONLY */ static inline uint32_t tb_hash_func(tb_page_addr_t phys_pc, vaddr pc, diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index c6619f5b98..929af1f64c 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -116,7 +116,7 @@ static int tcg_init_machine(MachineState *ms) tb_htable_init(); tcg_init(s->tb_size * MiB, s->splitwx_enabled, max_cpus); -#if defined(CONFIG_SOFTMMU) +#if !defined(CONFIG_USER_ONLY) /* * There's no guest base to take into account, so go ahead and * initialize the prologue now.