From patchwork Fri Apr 12 16:08:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 788291 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp793864wrm; Fri, 12 Apr 2024 09:10:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX6c8hAWOcvIkZgpgbpXRMyrK8rYtjnhl38cK1AW0TErY1EePfQYqmvP7v8t4hFC9+RKKwrYTlHzwiQPtXYBsPC X-Google-Smtp-Source: AGHT+IEerTsJu6AnCsFqhSsjLplWqHZqkHgEggvgE4AHjI/Cwp0y49zUrIuHBJQvjy/VOZPhwBQ8 X-Received: by 2002:a05:6102:d8a:b0:47a:8aeb:5086 with SMTP id d10-20020a0561020d8a00b0047a8aeb5086mr1937246vst.21.1712938203002; Fri, 12 Apr 2024 09:10:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712938202; cv=none; d=google.com; s=arc-20160816; b=bMjNqsiHCMrCOUEtn1kYrJglpwWblQKXoPfICZIn6/YirjCuZGWUP448MHinlZ/8Q4 q4GvuH5myoX2MNWxtVQDSPvNs+RVIkbu2SoMM4zl0PGQvCGMMwrfmCbxIlOrDFavog7/ pXeTcSU0cJK1WyCeXqNrw4Axzy8v4HUjZnr5fwlYyoWKk0LucUQTh3Ro2+Lg3xOyNU1g M0pDdY2xvzYeZc4Wrw0+ncWesrBW3PDIW5GPc7NKnHz9UcJAXrlvqt6qecTG8Zl3sXu2 fmCuHQrhxi+xjt/tA1k5NfMopQCyrOWfKZMlK4nyQAWCsV8RpbBQtl66y9nrmhKB5Wkz lmMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dnNoCn2uuTyof16mVyr36WFsEKC/7L9I7y8bsz+RKho=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=tflMC7AenOFTsLShdJPFiC2X+wLroIYr9nXRlOK3xxpAQoWkvpkUY3SPaGmR1uvzdP w0CZMruoZmhmj///bheTlb2iEiSWo67aUyQV/sQmq6FY9fsmUNiDZb+V63nwWzsS9Xu6 QLc/tXxkeJqvvjwWoJz56q7T3yMiarBL9i70zmSKX57kCzxFKihYWp2/0/UB7NaeD+Vd 6zIrDdueSmO9k11RhVEgi+vbhPdhGH4HRM5cQ6UM36l8/qxizPXsOk9HDWn95v+M8rO3 gbkDuKumYxxXYbZ7SGvjjNsMCwwPHvCzDeVEujoKBU00egxl69u7vGOfjziO1aSUnh8/ 7hUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qN27ALbO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m17-20020a05610206d100b00479e36afd6fsi731081vsg.422.2024.04.12.09.10.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Apr 2024 09:10:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qN27ALbO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rvJRt-0001uO-G2; Fri, 12 Apr 2024 12:08:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvJRq-0001sj-2m for qemu-devel@nongnu.org; Fri, 12 Apr 2024 12:08:18 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rvJRm-0004ZE-G6 for qemu-devel@nongnu.org; Fri, 12 Apr 2024 12:08:17 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-41819c27ea3so116435e9.0 for ; Fri, 12 Apr 2024 09:08:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712938091; x=1713542891; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dnNoCn2uuTyof16mVyr36WFsEKC/7L9I7y8bsz+RKho=; b=qN27ALbOigZLK8Eod9grGvVpybJOgDXRrFFonbfhYKJf7hnXEHRjP7i06DgWywPx8u KwgMEGtRiF6VFU0c957cSWO7zuj6TA2boQzw6uPPFHsZIk3Gn0Nn4UuzwvYKfCNJRx4n 8KMt39BQEsHiZArk2qEy2qAMad1eLNv+6ZcsEmN+xqedlnSN/uqdwpPXjoG+rl/LRmRp H4W+BP+olg/OyE2c8l/gnsdj6ORBaa/qP6jcxXLdo04QZDiUvYb9MmjeHssMP6jr9Wth 0zKQRI+bUILpF4uNrZkuQM0YWc9TQzgSGPhDz2ws1Wsa2A6VottIlMXcyh2cohhNg36u yBKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712938091; x=1713542891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dnNoCn2uuTyof16mVyr36WFsEKC/7L9I7y8bsz+RKho=; b=BwEH9vdLLN4dIbh5HOleOEVOduyLd0Ad3+Yop8zA/wgDcki9zbBKnq0fM3eC245Uby uB2WE5wXegYqgfIla05nu/XtjdOfWUsoE2rHkLo1h33ZevJi5dAEFqgkkha1RtrQClDy rZU36bsxrLB+dalZL9GmB3wbAnTPCM15w64ndYtmbIIGVVOSOFBBBo9FMyJ2cyv/+ewy fJbfApRwUyeqwlSa+GP6w78vlvxS7cIrToTNsPz3m0P+UEBGLpNe6gYE1JhfL4DqRXee l7BNkciItcsbHJZIRh/7QXlrK3PbhTo51yGbp4RojBQEiRowOBnqh5YdGQuVtZmLH5Hw wxaA== X-Gm-Message-State: AOJu0YyMZOmNMEoxh31Kt/XTZPvYFoPfPRKiNjVxc/IVgXiHDe+i34tQ 6yO32g2RWI+SfMKsY7IH5fUwOChQzpnulkvGr6RdrBRExa7jMIpRIlGvpPj5itJPTkh8EwkofLR l X-Received: by 2002:a5d:6841:0:b0:346:bbd8:dd07 with SMTP id o1-20020a5d6841000000b00346bbd8dd07mr1785319wrw.30.1712938091057; Fri, 12 Apr 2024 09:08:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id cr12-20020a05600004ec00b00341ce80ea66sm4582371wrb.82.2024.04.12.09.08.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 09:08:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 1/6] hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr Date: Fri, 12 Apr 2024 17:08:04 +0100 Message-Id: <20240412160809.1260625-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240412160809.1260625-1-peter.maydell@linaro.org> References: <20240412160809.1260625-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The npcm7xx_clk and npcm7xx_gcr device reset methods look at the ResetType argument and only handle RESET_TYPE_COLD, producing a warning if another reset type is passed. This is different from how every other three-phase-reset method we have works, and makes it difficult to add new reset types. A better pattern is "assume that any reset type you don't know about should be handled like RESET_TYPE_COLD"; switch these devices to do that. Then adding a new reset type will only need to touch those devices where its behaviour really needs to be different from the standard cold reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- hw/misc/npcm7xx_clk.c | 13 +++---------- hw/misc/npcm7xx_gcr.c | 12 ++++-------- 2 files changed, 7 insertions(+), 18 deletions(-) diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index ac1622c38aa..2098c85ee01 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -873,20 +873,13 @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values)); - switch (type) { - case RESET_TYPE_COLD: - memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); - s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - npcm7xx_clk_update_all_clocks(s); - return; - } - + memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); + s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + npcm7xx_clk_update_all_clocks(s); /* * A small number of registers need to be reset on a core domain reset, * but no such reset type exists yet. */ - qemu_log_mask(LOG_UNIMP, "%s: reset type %d not implemented.", - __func__, type); } static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c index 9252f9d1488..c4c4e246d7e 100644 --- a/hw/misc/npcm7xx_gcr.c +++ b/hw/misc/npcm7xx_gcr.c @@ -159,14 +159,10 @@ static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type) QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values)); - switch (type) { - case RESET_TYPE_COLD: - memcpy(s->regs, cold_reset_values, sizeof(s->regs)); - s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron; - s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr; - s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3; - break; - } + memcpy(s->regs, cold_reset_values, sizeof(s->regs)); + s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron; + s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr; + s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3; } static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)