From patchwork Tue Apr 30 12:28:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 793318 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp231567wrf; Tue, 30 Apr 2024 05:31:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUHSFIRhF1AJ4TO5MfTxxe0V2MLI43am9a+0i+noRSXS8hJqM8ajWk/BMjAsYZt4x2847Ak/kI0llJi3E+w3L5H X-Google-Smtp-Source: AGHT+IHeirXsfJHAaThMqO4AGYD7XzIK319mPNq8J0mCq8qjBehdIbT6HWlcgRh7FCCIDdiPkIlD X-Received: by 2002:a05:6102:c12:b0:47b:b086:7652 with SMTP id x18-20020a0561020c1200b0047bb0867652mr3138832vss.29.1714480261034; Tue, 30 Apr 2024 05:31:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714480261; cv=none; d=google.com; s=arc-20160816; b=MZbel39K54U5PIuw2iD0UmtFb+mrAZXYLxtxy4D4rbAnrTlJM6MDBQyV2/hCybwHA2 ju9TMcAA4+BJEvJXvRsU0iwthTY6xPX9SEKet6FaiZ/4bw6z9UoHg2yTFIltzriYcsla sp+bRmRhoJd/qDWSeVINMMF9Y6N10tkSK1yP1EEnC32LQ/ks+cCL7kSdt+6dMUMovS4U PFsKItjWbmYxAL4Huq2l950Kj4bUoNV3M8od2LKAww/ciFvg9U4M6aVWtVpFE7ED6wCi bA8BV3sVgWQy7epHA3rvzosKuZLeY/zCUyjRfmgZvmpoamUfMScHDDg/ZDmPbudq8XN9 Cyjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BBGkki3XoBfIeLSBwHuc796dXQHmu3Ot2VHczarNrMY=; fh=FpicyC1Jz/v4a6LtO5q/pqWquDN+5u5L8HIupeq3rHw=; b=PhfyHbl9kaPEc++cwufTi87JKylOKiSLVq8EA++RTAU22tCej86SmQ97lRpluxnGnN TVDg9fyYIeOrlBZat2ZpEvkPWWjH+THJRZ9089xzHJRPOFjA+h5PYXkTS7vBzooUdiM5 URJ8z002ZGlCRtRqXB3vfjqO5pqKTsr4uC1OobQtAUxDJ9vBO2XU5KxsBejD0PNhUHZ5 7zgAXI9UTQw34mEaYTITjVSeQcB4/HDb62uSyZMKNeJiK5Cg3o/dc44pm+tBnUymdj3B BL0f5w2Ybjssu24dBqNBK1s4kl83zjL4pHnbrdPNzUS3oCuhcGdH42/njek2y2nrqdcD iL1w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kqRLcn5Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k5-20020a67ef45000000b00476b2678ccesi4380029vsr.755.2024.04.30.05.31.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 30 Apr 2024 05:31:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kqRLcn5Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1mbn-0006zy-1H; Tue, 30 Apr 2024 08:29:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1mbb-0006k7-4p for qemu-devel@nongnu.org; Tue, 30 Apr 2024 08:29:07 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s1mbY-0001of-4I for qemu-devel@nongnu.org; Tue, 30 Apr 2024 08:29:05 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-a58872c07d8so1154699466b.0 for ; Tue, 30 Apr 2024 05:29:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714480141; x=1715084941; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BBGkki3XoBfIeLSBwHuc796dXQHmu3Ot2VHczarNrMY=; b=kqRLcn5YLQQQhtF8RBWNWErFNPj75UFb7cBIZq7h3uM6XBTHqCMROG10TniACieJNf S4zTOsuMgczfhyo2j+lJK6cO2QNIWJiZ/uo7aRNn51sgWgPchgTEgYnIpL8wVF9UI2F+ lDYUHV0bhlw9FU+JpCHSq9f6PVzCrp36V7oL3JPQifDqiLtUo8aT2z4NIdbln2JmISrA MYgAhUHp3Zmrsgvyj98Udg2GSPikcrL5bjpF42+Gd8gOB0YlYEtIleNNm5/ybyymIsWz e89tpqW6/gbup/lieMdn+yj6JMe1FgV9Ippr4Q4OegnNlMlypi1PyJMpjiz6CajTTR2W HkGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714480141; x=1715084941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BBGkki3XoBfIeLSBwHuc796dXQHmu3Ot2VHczarNrMY=; b=uMiu3ivuRt6s25WaSf+zeuljrZ1TCk1DI7v6RxnxpNKdqU3vMwxUb+Z5nTV6v1GdFN Ln4sfVVBRILOw3HyjWHh20o9SJx2H5qOws9i4+pHUjGEUzywvrQBHOo2V+HHLINS/qVx l2xh6/WKdjLs68bca23SUqCbM+uCe9FOJA2Z+ZTFUSmY01L5HKvDkInOPsAmVMdg9LZO hc1uZndJSMUT/7kQgEZIHhpB+aFbhEyKdnBa7gbVDGe/HQttpoYoMGqqniv3/RQtohYd s5WWDN3Enu/pBMFLyyNyqmEBHwu8MXYSGweW48uLfAfYv7dgRdY6y+vzcsoGyUlTRrqr LOcA== X-Gm-Message-State: AOJu0YyQ/azdRKOcVtvopJuhpkxDERnpKcAZJkS74qH9a9c1cwx7hteL EAppI9YFc/fPO0k2dlldYTLNgS3kkXTkXd2yjpU747fPchxNEqyNSoGfPnymSeYg3/luwqlUgUd V X-Received: by 2002:a17:907:1704:b0:a55:5698:3ea6 with SMTP id le4-20020a170907170400b00a5556983ea6mr2404261ejc.29.1714480141176; Tue, 30 Apr 2024 05:29:01 -0700 (PDT) Received: from m1x-phil.lan (mab78-h01-176-184-55-179.dsl.sta.abo.bbox.fr. [176.184.55.179]) by smtp.gmail.com with ESMTPSA id a7-20020a170906670700b00a522bef9f06sm15005420ejp.181.2024.04.30.05.28.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 30 Apr 2024 05:29:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Ilya Leoshkevich , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v3 09/13] accel/tcg: Move @iommu_notifiers from CPUState to TCG AccelCPUState Date: Tue, 30 Apr 2024 14:28:03 +0200 Message-ID: <20240430122808.72025-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240430122808.72025-1-philmd@linaro.org> References: <20240430122808.72025-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org @iommu_notifiers is specific to TCG system emulation, move it to AccelCPUState. Restrict TCG specific code in system/physmem.c, adding an empty stub for tcg_register_iommu_notifier(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-20-philmd@linaro.org> --- accel/tcg/vcpu-state.h | 3 +++ include/hw/core/cpu.h | 3 --- system/physmem.c | 37 ++++++++++++++++++++++++++++--------- 3 files changed, 31 insertions(+), 12 deletions(-) diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h index 5b09279140..51e54ca535 100644 --- a/accel/tcg/vcpu-state.h +++ b/accel/tcg/vcpu-state.h @@ -19,6 +19,9 @@ struct AccelCPUState { #ifdef CONFIG_USER_ONLY TaskState *ts; +#else + /* track IOMMUs whose translations we've cached in the TCG TLB */ + GArray *iommu_notifiers; #endif /* !CONFIG_USER_ONLY */ #ifdef CONFIG_PLUGIN diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 97a0baf874..f3cbb944eb 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -539,9 +539,6 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; - /* track IOMMUs whose translations we've cached in the TCG TLB */ - GArray *iommu_notifiers; - /* * MUST BE LAST in order to minimize the displacement to CPUArchState. */ diff --git a/system/physmem.c b/system/physmem.c index 44e477a1a5..1e003e42bb 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -27,6 +27,8 @@ #include "qemu/madvise.h" #ifdef CONFIG_TCG +#include "exec/translate-all.h" +#include "accel/tcg/vcpu-state.h" #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ @@ -578,6 +580,8 @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, return mr; } +#ifdef CONFIG_TCG + typedef struct TCGIOMMUNotifier { IOMMUNotifier n; MemoryRegion *mr; @@ -614,17 +618,20 @@ static void tcg_register_iommu_notifier(CPUState *cpu, TCGIOMMUNotifier *notifier = NULL; int i; - for (i = 0; i < cpu->iommu_notifiers->len; i++) { - notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); + for (i = 0; i < cpu->accel->iommu_notifiers->len; i++) { + notifier = g_array_index(cpu->accel->iommu_notifiers, + TCGIOMMUNotifier *, i); if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) { break; } } - if (i == cpu->iommu_notifiers->len) { + if (i == cpu->accel->iommu_notifiers->len) { /* Not found, add a new entry at the end of the array */ - cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1); + cpu->accel->iommu_notifiers = g_array_set_size(cpu->accel->iommu_notifiers, + i + 1); notifier = g_new0(TCGIOMMUNotifier, 1); - g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier; + g_array_index(cpu->accel->iommu_notifiers, + TCGIOMMUNotifier *, i) = notifier; notifier->mr = mr; notifier->iommu_idx = iommu_idx; @@ -656,19 +663,31 @@ void tcg_iommu_free_notifier_list(CPUState *cpu) int i; TCGIOMMUNotifier *notifier; - for (i = 0; i < cpu->iommu_notifiers->len; i++) { - notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); + for (i = 0; i < cpu->accel->iommu_notifiers->len; i++) { + notifier = g_array_index(cpu->accel->iommu_notifiers, + TCGIOMMUNotifier *, i); memory_region_unregister_iommu_notifier(notifier->mr, ¬ifier->n); g_free(notifier); } - g_array_free(cpu->iommu_notifiers, true); + g_array_free(cpu->accel->iommu_notifiers, true); } void tcg_iommu_init_notifier_list(CPUState *cpu) { - cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *)); + cpu->accel->iommu_notifiers = g_array_new(false, true, + sizeof(TCGIOMMUNotifier *)); } +#else + +static void tcg_register_iommu_notifier(CPUState *cpu, + IOMMUMemoryRegion *iommu_mr, + int iommu_idx) +{ +} + +#endif + /* Called from RCU critical section */ MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,