From patchwork Tue Apr 30 12:28:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 793311 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp231064wrf; Tue, 30 Apr 2024 05:30:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXuOjbMkSAj8MswhqU4V4h1ZxsakIMu3zUTk/PgxX2zXoF8GzsMSmVJbKs9OSkX2k/vw+k04MB8ZIasZLUrK3/b X-Google-Smtp-Source: AGHT+IGXotABKwrTRZekxWdYj4xdeNWT7DwFP8njm9xv3QEqIr1/66FLWTgUTVjgg7JjxcLG9bKd X-Received: by 2002:a05:622a:1a0e:b0:43a:bd5b:2558 with SMTP id f14-20020a05622a1a0e00b0043abd5b2558mr10131312qtb.36.1714480200247; Tue, 30 Apr 2024 05:30:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714480200; cv=none; d=google.com; s=arc-20160816; b=eAY9VyHHXAUlDoW5fW2yFd2/nzn8VQdeR+XciTmv47fUBrJXoiJB9mUMhxYxx/dVcI BcJY43MFPy2r7qZkA9s/eN5fXRsdOE3Frfn6UnmRI0CCiiPOLjaTZp4nmynGzT/AspXi HU3HcL+aM2aBukGb2MZxYEurC0gBlJXM3gkln5KZdY7I1G2CO3dCJI/Q5yWEhneQXg4E ok3y4bqlDmKKiA6mvUIwpxjmDy79Tgsrf7RIu/2IWgd6YM4+Tv/1DhPdEusGb7kMkURJ /ivF3yBaF2Ef090AA4yqMwYPiziJIK7pocP/3cj/XpzP3op+fqXTPPpE0SxmyPgDOttD BNpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fzwfr/wTeB46SuXanUOeFcxVvZg85d/Fb55ijGv7nN4=; fh=FpicyC1Jz/v4a6LtO5q/pqWquDN+5u5L8HIupeq3rHw=; b=du4gtHRMn2laG2XKuPP0Ya26mQlnZbOYm7iFrMBic7E+kWvfy1fkITlhkIdQC/pJ0J 2L+bI4dQHgrzlK53Y0ZbOwqXZIykpaxZveUFwjcyag+JIqwPcDB9g2CDvlwu+nPQ4bkO Zt2aKboIldxNptef84e8UUuoXyphMFUecw/2TsZwyeHYqPmfJqO+ZUyoBKIXg5DvwzHF a6hDZf4lddjuukrK22Gq0ofFBnDkoiQA3Aco6PQzLH1VyrZO9569YNW3pLdJNtWXTV2z gxNnS2SG7a/nRU+qmsVe+gt8c39YQI/iSt2YExufhaXz1/Fq0tL3rRzoL52R1R+B0SUE hRUw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XkW0i1vL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ge26-20020a05622a5c9a00b00439755ce804si24691151qtb.231.2024.04.30.05.30.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 30 Apr 2024 05:30:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XkW0i1vL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1mcC-0007fg-EO; Tue, 30 Apr 2024 08:29:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1mbv-0007Es-MX for qemu-devel@nongnu.org; Tue, 30 Apr 2024 08:29:28 -0400 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s1mbr-0001pT-88 for qemu-devel@nongnu.org; Tue, 30 Apr 2024 08:29:27 -0400 Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-57222fc625aso6361680a12.3 for ; Tue, 30 Apr 2024 05:29:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714480158; x=1715084958; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fzwfr/wTeB46SuXanUOeFcxVvZg85d/Fb55ijGv7nN4=; b=XkW0i1vL2J7FLbpXfazTF2XdHDNNOdaj282PI2K3bfSz2kkddawPZTQSI64GXU6SMq tTK4ICh+vYSPjtoY/XZeV/KjEbAh2DoLTfpybGQ5YGKsvRz4KQzBl9vlWEhGgGEeu1XB bmZxRcnZWcRbPZg8uaLWxibFeEcS9eRmVOrHeR3RuZZysiP/fpqkGupqew3uPp4kt6Cw BERFkXK2xmkotGbviLEfpd0ni6Rnn3i8hG0cKk1OVA6gQjv3WWcJfl33nGGiztgwyGox ZTk3dbwYKThMmeJv0n/5xDJwAIgL+jsHuELHjvGsi1l6rWCDy0e1fP4rx8RtVFc7zXmJ M26Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714480158; x=1715084958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fzwfr/wTeB46SuXanUOeFcxVvZg85d/Fb55ijGv7nN4=; b=AlSWz3EqFFSmf7L5zX+qzDtz26Z9cgty1TAoeOeKNjMUlCKPdUhr5j/rBVHLxHBD+a f3w5SL1WthlNsTUBGYtPLnQMkVOA0p7PZvgDYvWYnUkD5Yvw7S8CcFqicTETRdhtybqZ grzgAoy83G5hjNVdPxhHGxQkI1cyXASpk1UF1v689czr4wmsedorPW4iLBMk6jX6tc4Q TaoN0MHwHvF/58lk1dSQCcOzU+qQRKaG1efwLVi4Rl3MuxmYePpNIFNjreZ3XjjMMb9N HyYxBAlrKmUjKm4A+Jz7m+wsxmD+Bw+XYyJStNRnz/m2tGb5ajEohHhwT0TdYAarMPkU jTvw== X-Gm-Message-State: AOJu0Yy7zRwUoGhRaJUCRPiBUfke6Qd7I6dzbUCKcJiv0dKo0FDJutfS bfF5V3F5yCHr51V2YbLuM1KWgr2AdIma1l7vPrWWKzRYp3JsN0hPXuPvPKsCr2WMUiX/NlrMOke Z X-Received: by 2002:a50:8e0f:0:b0:571:bed1:3a36 with SMTP id 15-20020a508e0f000000b00571bed13a36mr11183710edw.38.1714480158255; Tue, 30 Apr 2024 05:29:18 -0700 (PDT) Received: from m1x-phil.lan (mab78-h01-176-184-55-179.dsl.sta.abo.bbox.fr. [176.184.55.179]) by smtp.gmail.com with ESMTPSA id ev9-20020a056402540900b005725de35790sm4419784edb.61.2024.04.30.05.29.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 30 Apr 2024 05:29:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Johansson , Ilya Leoshkevich , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v3 12/13] accel/tcg: Move icount fields from CPUState to TCG AccelCPUState Date: Tue, 30 Apr 2024 14:28:06 +0200 Message-ID: <20240430122808.72025-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240430122808.72025-1-philmd@linaro.org> References: <20240430122808.72025-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philmd@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both @icount_budget and @icount_extra fields are specific to TCG accelerator, move them to its AccelCPUState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-25-philmd@linaro.org> --- accel/tcg/vcpu-state.h | 4 ++++ include/hw/core/cpu.h | 3 --- accel/tcg/cpu-exec.c | 14 +++++++------- accel/tcg/icount-common.c | 7 ++++--- accel/tcg/tcg-accel-ops-icount.c | 14 +++++++------- accel/tcg/tcg-accel-ops.c | 1 + hw/core/cpu-common.c | 1 - 7 files changed, 23 insertions(+), 21 deletions(-) diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h index 008fe847b4..716a0119c4 100644 --- a/accel/tcg/vcpu-state.h +++ b/accel/tcg/vcpu-state.h @@ -11,6 +11,7 @@ /** * AccelCPUState: vCPU fields specific to TCG accelerator * @cflags: Pre-computed cflags for this cpu. + * @icount_extra: Instructions until next timer event. * @plugin_state: per-CPU plugin state */ struct AccelCPUState { @@ -22,6 +23,9 @@ struct AccelCPUState { #ifdef CONFIG_USER_ONLY TaskState *ts; #else + int64_t icount_budget; + int64_t icount_extra; + /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; #endif /* !CONFIG_USER_ONLY */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e546e67f4d..f06bb1e93a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -409,7 +409,6 @@ struct qemu_work_item; * @unplug: Indicates a pending CPU unplug request. * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU * @singlestep_enabled: Flags for single-stepping. - * @icount_extra: Instructions until next timer event. * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the * AddressSpaces this CPU has) * @num_ases: number of CPUAddressSpaces in @cpu_ases @@ -470,8 +469,6 @@ struct CPUState { /* updates protected by BQL */ uint32_t interrupt_request; int singlestep_enabled; - int64_t icount_budget; - int64_t icount_extra; uint64_t random_seed; QemuMutex work_mutex; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 49b4b57a56..a491278082 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -75,7 +75,7 @@ static void align_clocks(SyncClocks *sc, CPUState *cpu) return; } - cpu_icount = cpu->icount_extra + cpu->neg.icount_decr.u16.low; + cpu_icount = cpu->accel->icount_extra + cpu->neg.icount_decr.u16.low; sc->diff_clk += icount_to_ns(sc->last_cpu_icount - cpu_icount); sc->last_cpu_icount = cpu_icount; @@ -126,7 +126,7 @@ static void init_delay_params(SyncClocks *sc, CPUState *cpu) sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock; sc->last_cpu_icount - = cpu->icount_extra + cpu->neg.icount_decr.u16.low; + = cpu->accel->icount_extra + cpu->neg.icount_decr.u16.low; if (sc->diff_clk < max_delay) { max_delay = sc->diff_clk; } @@ -719,7 +719,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (cpu->exception_index < 0) { #ifndef CONFIG_USER_ONLY if (replay_has_exception() - && cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0) { + && cpu->neg.icount_decr.u16.low + cpu->accel->icount_extra == 0) { /* Execute just one insn to trigger exception pending in the log */ cpu->accel->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) | CF_NOIRQ | 1; @@ -790,7 +790,7 @@ static inline bool icount_exit_request(CPUState *cpu) if (!(cpu->accel->cflags_next_tb == -1 || cpu->accel->cflags_next_tb & CF_USE_ICOUNT)) { return false; } - return cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0; + return cpu->neg.icount_decr.u16.low + cpu->accel->icount_extra == 0; #endif } @@ -942,9 +942,9 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, /* Ensure global icount has gone forward */ icount_update(cpu); /* Refill decrementer and continue execution. */ - int32_t insns_left = MIN(0xffff, cpu->icount_budget); + int32_t insns_left = MIN(0xffff, cpu->accel->icount_budget); cpu->neg.icount_decr.u16.low = insns_left; - cpu->icount_extra = cpu->icount_budget - insns_left; + cpu->accel->icount_extra = cpu->accel->icount_budget - insns_left; /* * If the next tb has more instructions than we have left to @@ -953,7 +953,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, */ if (insns_left > 0 && insns_left < tb->icount) { assert(insns_left <= CF_COUNT_MASK); - assert(cpu->icount_extra == 0); + assert(cpu->accel->icount_extra == 0); cpu->accel->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left; } #endif diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index 8d3d3a7e9d..ff503f8e96 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -38,6 +38,7 @@ #include "sysemu/cpu-timers.h" #include "sysemu/cpu-throttle.h" #include "sysemu/cpu-timers-internal.h" +#include "accel/tcg/vcpu-state.h" /* * ICOUNT: Instruction Counter @@ -71,8 +72,8 @@ static void icount_enable_adaptive(void) */ static int64_t icount_get_executed(CPUState *cpu) { - return (cpu->icount_budget - - (cpu->neg.icount_decr.u16.low + cpu->icount_extra)); + return (cpu->accel->icount_budget - + (cpu->neg.icount_decr.u16.low + cpu->accel->icount_extra)); } /* @@ -83,7 +84,7 @@ static int64_t icount_get_executed(CPUState *cpu) static void icount_update_locked(CPUState *cpu) { int64_t executed = icount_get_executed(cpu); - cpu->icount_budget -= executed; + cpu->accel->icount_budget -= executed; qatomic_set_i64(&timers_state.qemu_icount, timers_state.qemu_icount + executed); diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c index 9e1ae66f65..75073ec23f 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -112,16 +112,16 @@ void icount_prepare_for_run(CPUState *cpu, int64_t cpu_budget) * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt */ g_assert(cpu->neg.icount_decr.u16.low == 0); - g_assert(cpu->icount_extra == 0); + g_assert(cpu->accel->icount_extra == 0); replay_mutex_lock(); - cpu->icount_budget = MIN(icount_get_limit(), cpu_budget); - insns_left = MIN(0xffff, cpu->icount_budget); + cpu->accel->icount_budget = MIN(icount_get_limit(), cpu_budget); + insns_left = MIN(0xffff, cpu->accel->icount_budget); cpu->neg.icount_decr.u16.low = insns_left; - cpu->icount_extra = cpu->icount_budget - insns_left; + cpu->accel->icount_extra = cpu->accel->icount_budget - insns_left; - if (cpu->icount_budget == 0) { + if (cpu->accel->icount_budget == 0) { /* * We're called without the BQL, so must take it while * we're calling timer handlers. @@ -139,8 +139,8 @@ void icount_process_data(CPUState *cpu) /* Reset the counters */ cpu->neg.icount_decr.u16.low = 0; - cpu->icount_extra = 0; - cpu->icount_budget = 0; + cpu->accel->icount_extra = 0; + cpu->accel->icount_budget = 0; replay_account_executed_instructions(); diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index d9132a5835..3b28cab0b5 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -89,6 +89,7 @@ static void tcg_cpu_reset_hold(CPUState *cpu) qatomic_set(&cpu->neg.icount_decr.u32, 0); cpu->neg.can_do_io = true; + cpu->accel->icount_extra = 0; cpu->accel->cflags_next_tb = -1; } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index b6631b6245..e03d31876f 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -121,7 +121,6 @@ static void cpu_common_reset_hold(Object *obj, ResetType type) cpu->interrupt_request = 0; cpu->halted = cpu->start_powered_off; cpu->mem_io_pc = 0; - cpu->icount_extra = 0; cpu->exception_index = -1; cpu->crash_occurred = false;