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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id n15-20020a170902e54f00b001e4d22f828fsm5197859plf.33.2024.05.04.08.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 May 2024 08:39:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU Date: Sat, 4 May 2024 08:39:18 -0700 Message-Id: <20240504153926.357845-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240504153926.357845-1-richard.henderson@linaro.org> References: <20240504153926.357845-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ALPHA_CPU has a dynamic object type assert, which is unnecessary considering that these are all class hooks. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240503072014.24751-2-philmd@linaro.org> --- target/alpha/cpu.c | 15 ++++++--------- target/alpha/helper.c | 8 ++++---- 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 05f9ee41e9..f98d022671 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -28,25 +28,22 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { - AlphaCPU *cpu = ALPHA_CPU(cs); - - cpu->env.pc = value; + CPUAlphaState *env = cpu_env(cs); + env->pc = value; } static vaddr alpha_cpu_get_pc(CPUState *cs) { - AlphaCPU *cpu = ALPHA_CPU(cs); - - return cpu->env.pc; + CPUAlphaState *env = cpu_env(cs); + return env->pc; } static void alpha_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - AlphaCPU *cpu = ALPHA_CPU(cs); - - cpu->env.pc = data[0]; + CPUAlphaState *env = cpu_env(cs); + env->pc = data[0]; } static bool alpha_cpu_has_work(CPUState *cs) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index d6d4353edd..c5e4958f8b 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -124,7 +124,7 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = cpu_env(cs); target_ulong mmcsr, cause; /* Assuming !maperr, infer the missing protection. */ @@ -155,9 +155,9 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, } /* Record the arguments that PALcode would give to the kernel. */ - cpu->env.trap_arg0 = address; - cpu->env.trap_arg1 = mmcsr; - cpu->env.trap_arg2 = cause; + env->trap_arg0 = address; + env->trap_arg1 = mmcsr; + env->trap_arg2 = cause; } #else /* Returns the OSF/1 entMM failure indication, or -1 on success. */