From patchwork Thu May 23 15:34:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 798429 Delivered-To: patch@linaro.org Received: by 2002:a5d:6a47:0:b0:354:fb4b:99cd with SMTP id t7csp287887wrw; Thu, 23 May 2024 08:42:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVHqIuEUPXpdekfiSm/nUwBbDHA3T9zD48z3XGz6t0DBq8pyB1LNdOhEjrw1z8LYDpicVszapaQlDch6WA9FV2T X-Google-Smtp-Source: AGHT+IEs0b/2QrsJu2fXy7rHhLNYg41aUCbgDTzB2mvj9FJZf5uty+0kskDHmdsm84VQTV8XVCxM X-Received: by 2002:a05:6808:191b:b0:3c9:d067:1de9 with SMTP id 5614622812f47-3cdb48f0642mr6449908b6e.34.1716478934652; Thu, 23 May 2024 08:42:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1716478934; cv=none; d=google.com; s=arc-20160816; b=yzKmi0JoNYY00nP2+wJJKe1jGsl8RCpBX3eTsu/iM1RKuvNqM1itgQlfHETFK4yDuO bx/Hdla+4ml5ZWmhuxgFaFC8Kq9jhNm9CWY6ADlJZUfpNZ/hRRPe2qpt50eLPRfN5pFC kS5QprXWEN1GY4Kw7vh/vsTtGSIywd7BOplePHrtZwugwGkpNvCp8HebBYb4Ley0zlUw 6w+9DSDDai45UfX/JZD+X/vBg8iltw+UNmn79gnN5sdjEMowwtK7P6t0sopLuYDX7Rzh it7v7POtgYm8myDJbpPFNkyFFLF29FcAVkTLtSBxZ5q/fYJtfQtqv+1g0/0GGKrLx/0E cjsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7wVMNIYRSiagShlb5ApLejiYbezLHM8Fo5W7lCc+EkQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=iGthL/6eJCUCtyvsHe/BgnCQC/D4/tGgfljWeGV8WaIkSVwHnmt7OC470BYIqluETR /JLWB338io5Ti2bZIxmrJ3EGjMtzs9Yu/yJNAeaQgaz8jDa32uVZMJJjfZQcYCtlJLuM 8aChivKjjkTah6Z6spRdB4ZhWXzW08a0/fsG9Yx3sl3TjHHE+thIep7R5KfifBlz2h4s yXvxkpmwrLgFFLi3NVOdZT0nbII+tOgevZd2WLET/ClzvmC2N10G9JQ80pticzc7fcc8 TncDVRjn+/fE6kP7dK/yUPaQgWu9yTav5tIpFDQM7MYLaotpaXqBVpTJclREZK6LWytd CezA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=clJJTDSJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-792c23b3e53si120160685a.237.2024.05.23.08.42.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 May 2024 08:42:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=clJJTDSJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sAATf-00082N-Kc; Thu, 23 May 2024 11:35:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sAATW-0007sr-KJ for qemu-devel@nongnu.org; Thu, 23 May 2024 11:35:28 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sAATT-0002UN-HR for qemu-devel@nongnu.org; Thu, 23 May 2024 11:35:25 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4200ee78f35so39486715e9.1 for ; Thu, 23 May 2024 08:35:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716478516; x=1717083316; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7wVMNIYRSiagShlb5ApLejiYbezLHM8Fo5W7lCc+EkQ=; b=clJJTDSJ4k7C4G8ss+SqB7Zgl3cZtQ56Enraiq5aQ7xrZeVnlAQTWZeAcdzpGYtTnJ p2+1zA2EdIRAmRXHmZj5VA7XQ0U63jjT/C0YDKpj2sh4Z3lgVRYKbh7TNo+9EbtL3lG0 SN8ctZfRoEb8Gt0yYhTwoeb8JgvJpBaQLaxDnU8jLKIANqr1VnprCRwhnoRI6DqWm+2P gV2gWW0SNRJFK07VTfED71dQmVG+XL8c6pxKmjpXwsKq4ehdZWIZXjde9+8vvC9O1Ng0 GJy6gbV95lg2iluEY6mJBBvWKgrVAg3ALWfqy3DvfE9ZEfYrkL4gDmbBqhiwy3nYODPT RKtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716478516; x=1717083316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7wVMNIYRSiagShlb5ApLejiYbezLHM8Fo5W7lCc+EkQ=; b=LIc55nHRQ7EDMDvFpOSsQZY95q8WZDPPF/gNUxeNNU/iR8pqkeN3mkKVnLp6LR5g7j cydCexkGdslaAqOr2r5zBIthebzS+UDawE4L49AVfcJst0Dlo1hXFnYkdZjK6xkrxMLE ILCdVGNIvc5Iq250WDSxFQzdESmttqkh/IXvSvEVLD8q7Di4V5xtuMZelA0FEUwLHZ5V kQi98zCp+O6q6XXoCKVLT//5ylg49EbIEb2Ub6t3pvNiTsXA829oBFQL6/BJG491DM/O QOp2W1gVNM1eO5e5yOtMl5L7wSt/wd79ojhsxkJyjg1QC0XgQfi/+9EoJdzU72/VX6yk A1JA== X-Gm-Message-State: AOJu0Yx0Ga72GGWBtJmApNppW7SIj5b25vhomX0Y1M8SIicjGC8sO9nC sEIfW+P/d38v7LcYJGrDli5HxKMVhqodG3ZwMUvzfzTIOlfBxc+CXOFoGgwNVktnnC7shvatiol G X-Received: by 2002:a5d:6a8a:0:b0:355:3f6:1ba4 with SMTP id ffacd0b85a97d-35503f61ca5mr354369f8f.64.1716478515734; Thu, 23 May 2024 08:35:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-354df9b51f7sm3888255f8f.59.2024.05.23.08.35.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 08:35:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/37] target/arm: Convert Cryptographic 3-register, imm2 to decodetree Date: Thu, 23 May 2024 16:34:45 +0100 Message-Id: <20240523153505.2900433-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523153505.2900433-1-peter.maydell@linaro.org> References: <20240523153505.2900433-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20240506010403.6204-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 10 ++++++++ target/arm/tcg/translate-a64.c | 43 ++++++++++------------------------ 2 files changed, 22 insertions(+), 31 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index ef6902e86a5..1292312a7f9 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -644,3 +644,13 @@ SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 + +### Cryptographic three-register, imm2 + +&crypto3i rd rn rm imm +@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i + +SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i +SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i +SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i +SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index aa8d83efe1b..eea0943911a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4676,6 +4676,18 @@ static bool trans_SM3SS1(DisasContext *s, arg_SM3SS1 *a) return true; } +static bool do_crypto3i(DisasContext *s, arg_crypto3i *a, gen_helper_gvec_3 *fn) +{ + if (fp_access_check(s)) { + gen_gvec_op3_ool(s, true, a->rd, a->rn, a->rm, a->imm, fn); + } + return true; +} +TRANS_FEAT(SM3TT1A, aa64_sm3, do_crypto3i, a, gen_helper_crypto_sm3tt1a) +TRANS_FEAT(SM3TT1B, aa64_sm3, do_crypto3i, a, gen_helper_crypto_sm3tt1b) +TRANS_FEAT(SM3TT2A, aa64_sm3, do_crypto3i, a, gen_helper_crypto_sm3tt2a) +TRANS_FEAT(SM3TT2B, aa64_sm3, do_crypto3i, a, gen_helper_crypto_sm3tt2b) + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -13597,36 +13609,6 @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn) vec_full_reg_size(s)); } -/* Crypto three-reg imm2 - * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 - * +-----------------------+------+-----+------+--------+------+------+ - * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd | - * +-----------------------+------+-----+------+--------+------+------+ - */ -static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) -{ - static gen_helper_gvec_3 * const fns[4] = { - gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b, - gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b, - }; - int opcode = extract32(insn, 10, 2); - int imm2 = extract32(insn, 12, 2); - int rm = extract32(insn, 16, 5); - int rn = extract32(insn, 5, 5); - int rd = extract32(insn, 0, 5); - - if (!dc_isar_feature(aa64_sm3, s)) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]); -} - /* C3.6 Data processing - SIMD, inc Crypto * * As the decode gets a little complex we are using a table based @@ -13656,7 +13638,6 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, { 0xce800000, 0xffe00000, disas_crypto_xar }, - { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 },