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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2bf5f6155b6sm4943761a91.29.2024.05.26.12.36.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:36:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH RISU v2 13/13] sparc64: Add VIS4 instructions Date: Sun, 26 May 2024 12:36:37 -0700 Message-Id: <20240526193637.459064-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526193637.459064-1-richard.henderson@linaro.org> References: <20240526193637.459064-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- sparc64.risu | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index 271fee0..1022a62 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -250,3 +250,49 @@ MOVxTOd VIS3 10 rd:5 110110 00000 1 0001 1000 rs2:5 \ FPMADDX IMA 10 rd:5 110111 rs1:5 rs3:5 0000 rs2:5 FPMADDXHI IMA 10 rd:5 110111 rs1:5 rs3:5 0100 rs2:5 + +# +# VIS4 +# + +SUBXC VIS4 10 rd:5 110110 rs1:5 0 0100 00 cc 1 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } + +FPADD8 VIS4 10 rd:5 110110 rs1:5 1 0010 0100 rs2:5 +FPADDS8 VIS4 10 rd:5 110110 rs1:5 1 0010 0110 rs2:5 +FPADDUS8 VIS4 10 rd:5 110110 rs1:5 1 0010 0111 rs2:5 +FPADDUS16 VIS4 10 rd:5 110110 rs1:5 1 0010 0011 rs2:5 +FPSUB8 VIS4 10 rd:5 110110 rs1:5 1 0101 0100 rs2:5 +FPSUBS8 VIS4 10 rd:5 110110 rs1:5 1 0101 0110 rs2:5 +FPSUBUS8 VIS4 10 rd:5 110110 rs1:5 1 0101 0111 rs2:5 +FPSUBUS16 VIS4 10 rd:5 110110 rs1:5 1 0101 0011 rs2:5 + +FPMIN8 VIS4 10 rd:5 110110 rs1:5 1 0001 1010 rs2:5 +FPMIN16 VIS4 10 rd:5 110110 rs1:5 1 0001 1011 rs2:5 +FPMIN32 VIS4 10 rd:5 110110 rs1:5 1 0001 1100 rs2:5 +FPMINU8 VIS4 10 rd:5 110110 rs1:5 1 0101 1010 rs2:5 +FPMINU16 VIS4 10 rd:5 110110 rs1:5 1 0101 1011 rs2:5 +FPMINU32 VIS4 10 rd:5 110110 rs1:5 1 0101 1100 rs2:5 + +FPMAX8 VIS4 10 rd:5 110110 rs1:5 1 0001 1101 rs2:5 +FPMAX16 VIS4 10 rd:5 110110 rs1:5 1 0001 1110 rs2:5 +FPMAX32 VIS4 10 rd:5 110110 rs1:5 1 0001 1111 rs2:5 +FPMAXU8 VIS4 10 rd:5 110110 rs1:5 1 0101 1101 rs2:5 +FPMAXU16 VIS4 10 rd:5 110110 rs1:5 1 0101 1110 rs2:5 +FPMAXU32 VIS4 10 rd:5 110110 rs1:5 1 0101 1111 rs2:5 + +FPCMPLE8 VIS4 10 rd:5 110110 rs1:5 0 0011 0100 rs2:5 \ + !constraints { reg_ok($rd) } +FPCMPGT8 VIS4 10 rd:5 110110 rs1:5 0 0011 1100 rs2:5 \ + !constraints { reg_ok($rd) } +FPCMPULE16 VIS4 10 rd:5 110110 rs1:5 1 0010 1110 rs2:5 \ + !constraints { reg_ok($rd) } +FPCMPUGT16 VIS4 10 rd:5 110110 rs1:5 1 0010 1011 rs2:5 \ + !constraints { reg_ok($rd) } +FPCMPULE32 VIS4 10 rd:5 110110 rs1:5 1 0010 1111 rs2:5 \ + !constraints { reg_ok($rd) } +FPCMPUGT32 VIS4 10 rd:5 110110 rs1:5 1 0010 1100 rs2:5 \ + !constraints { reg_ok($rd) } + +FALIGNDATAi VIS4 10 rd:5 110110 rs1:5 0 0100 1001 rs2:5 \ + !constraints { reg_ok($rs1); }