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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fd6d7598sm3942958b3a.220.2024.05.26.17.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 17:50:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Paolo Bonzini Subject: [PULL 24/28] target/i386: Convert do_xsave to X86Access Date: Sun, 26 May 2024 17:49:57 -0700 Message-Id: <20240527005001.642825-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240527005001.642825-1-richard.henderson@linaro.org> References: <20240527005001.642825-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- linux-user/i386/signal.c | 2 +- target/i386/tcg/fpu_helper.c | 72 +++++++++++++++++++++--------------- 2 files changed, 43 insertions(+), 31 deletions(-) diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index e716ec8989..ab760db5ea 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -329,7 +329,7 @@ static void xsave_sigcontext(CPUX86State *env, /* Zero the header, XSAVE *adds* features to an existing save state. */ memset(fxstate + 1, 0, sizeof(X86XSaveHeader)); - cpu_x86_xsave(env, xstate_addr, -1); + cpu_x86_xsave(env, xstate_addr, env->xcr0); __put_user(TARGET_FP_XSTATE_MAGIC1, &sw->magic1); __put_user(extended_size, &sw->extended_size); diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index a09d6aaf07..f5748b72b8 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -2668,47 +2668,38 @@ static uint64_t get_xinuse(CPUX86State *env) return inuse; } -static void do_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm, - uint64_t inuse, uint64_t opt, uintptr_t ra) +static void do_xsave_access(X86Access *ac, target_ulong ptr, uint64_t rfbm, + uint64_t inuse, uint64_t opt) { uint64_t old_bv, new_bv; - X86Access ac; - unsigned size; - - /* Never save anything not enabled by XCR0. */ - rfbm &= env->xcr0; - opt &= rfbm; - - size = xsave_area_size(opt, false); - access_prepare(&ac, env, ptr, size, MMU_DATA_STORE, ra); if (opt & XSTATE_FP_MASK) { - do_xsave_fpu(&ac, ptr); + do_xsave_fpu(ac, ptr); } if (rfbm & XSTATE_SSE_MASK) { /* Note that saving MXCSR is not suppressed by XSAVEOPT. */ - do_xsave_mxcsr(&ac, ptr); + do_xsave_mxcsr(ac, ptr); } if (opt & XSTATE_SSE_MASK) { - do_xsave_sse(&ac, ptr); + do_xsave_sse(ac, ptr); } if (opt & XSTATE_YMM_MASK) { - do_xsave_ymmh(&ac, ptr + XO(avx_state)); + do_xsave_ymmh(ac, ptr + XO(avx_state)); } if (opt & XSTATE_BNDREGS_MASK) { - do_xsave_bndregs(&ac, ptr + XO(bndreg_state)); + do_xsave_bndregs(ac, ptr + XO(bndreg_state)); } if (opt & XSTATE_BNDCSR_MASK) { - do_xsave_bndcsr(&ac, ptr + XO(bndcsr_state)); + do_xsave_bndcsr(ac, ptr + XO(bndcsr_state)); } if (opt & XSTATE_PKRU_MASK) { - do_xsave_pkru(&ac, ptr + XO(pkru_state)); + do_xsave_pkru(ac, ptr + XO(pkru_state)); } /* Update the XSTATE_BV field. */ - old_bv = access_ldq(&ac, ptr + XO(header.xstate_bv)); + old_bv = access_ldq(ac, ptr + XO(header.xstate_bv)); new_bv = (old_bv & ~rfbm) | (inuse & rfbm); - access_stq(&ac, ptr + XO(header.xstate_bv), new_bv); + access_stq(ac, ptr + XO(header.xstate_bv), new_bv); } static void do_xsave_chk(CPUX86State *env, target_ulong ptr, uintptr_t ra) @@ -2724,22 +2715,32 @@ static void do_xsave_chk(CPUX86State *env, target_ulong ptr, uintptr_t ra) } } -void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm) +static void do_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm, + uint64_t inuse, uint64_t opt, uintptr_t ra) { - uintptr_t ra = GETPC(); + X86Access ac; + unsigned size; do_xsave_chk(env, ptr, ra); - do_xsave(env, ptr, rfbm, get_xinuse(env), -1, ra); + + /* Never save anything not enabled by XCR0. */ + rfbm &= env->xcr0; + opt &= rfbm; + size = xsave_area_size(opt, false); + + access_prepare(&ac, env, ptr, size, MMU_DATA_STORE, ra); + do_xsave_access(&ac, ptr, rfbm, inuse, opt); +} + +void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm) +{ + do_xsave(env, ptr, rfbm, get_xinuse(env), rfbm, GETPC()); } void helper_xsaveopt(CPUX86State *env, target_ulong ptr, uint64_t rfbm) { - uintptr_t ra = GETPC(); - uint64_t inuse; - - do_xsave_chk(env, ptr, ra); - inuse = get_xinuse(env); - do_xsave(env, ptr, rfbm, inuse, inuse, ra); + uint64_t inuse = get_xinuse(env); + do_xsave(env, ptr, rfbm, inuse, inuse, GETPC()); } static void do_xrstor_fpu(X86Access *ac, target_ulong ptr) @@ -3049,7 +3050,18 @@ void cpu_x86_fxrstor(CPUX86State *env, target_ulong ptr) void cpu_x86_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm) { - do_xsave(env, ptr, rfbm, get_xinuse(env), -1, 0); + X86Access ac; + unsigned size; + + /* + * Since this is only called from user-level signal handling, + * we should have done the job correctly there. + */ + assert((rfbm & ~env->xcr0) == 0); + size = xsave_area_size(rfbm, false); + + access_prepare(&ac, env, ptr, size, MMU_DATA_STORE, 0); + do_xsave_access(&ac, ptr, rfbm, get_xinuse(env), rfbm); } void cpu_x86_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)