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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c28066d511sm1720915a91.9.2024.06.05.10.22.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 10:22:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/38] target/sparc: Fix helper_fmul8ulx16 Date: Wed, 5 Jun 2024 10:22:20 -0700 Message-Id: <20240605172253.356302-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605172253.356302-1-richard.henderson@linaro.org> References: <20240605172253.356302-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This operation returns the high 16 bits of a 24-bit multiply that has been sign-extended to 32 bits. Signed-off-by: Richard Henderson --- target/sparc/vis_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index f46fcf1f6a..41312deda4 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -174,10 +174,10 @@ uint64_t helper_fmul8ulx16(uint64_t src1, uint64_t src2) s.ll = src1; d.ll = src2; - d.VIS_W64(0) = do_ms16b(s.VIS_B64(0), d.VIS_SW64(0)); - d.VIS_W64(1) = do_ms16b(s.VIS_B64(2), d.VIS_SW64(1)); - d.VIS_W64(2) = do_ms16b(s.VIS_B64(4), d.VIS_SW64(2)); - d.VIS_W64(3) = do_ms16b(s.VIS_B64(6), d.VIS_SW64(3)); + d.VIS_W64(0) = (s.VIS_B64(0) * d.VIS_SW64(0) + 0x8000) >> 16; + d.VIS_W64(1) = (s.VIS_B64(2) * d.VIS_SW64(1) + 0x8000) >> 16; + d.VIS_W64(2) = (s.VIS_B64(4) * d.VIS_SW64(2) + 0x8000) >> 16; + d.VIS_W64(3) = (s.VIS_B64(6) * d.VIS_SW64(3) + 0x8000) >> 16; return d.ll; }