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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c91d3b9349sm5531698a91.37.2024.06.30.19.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jun 2024 19:51:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH 5/5] target/i386: Introduce cc_op_size Date: Sun, 30 Jun 2024 19:51:15 -0700 Message-Id: <20240701025115.1265117-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240701025115.1265117-1-richard.henderson@linaro.org> References: <20240701025115.1265117-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace arithmetic on cc_op with a helper function. Assert that the op has a size and that it is valid for the configuration. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 29 ++++++++++++++++++----------- target/i386/tcg/emit.c.inc | 3 ++- 2 files changed, 20 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e675afca47..e98bed0805 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -322,6 +322,16 @@ static uint8_t cc_op_live(CCOp op) g_assert_not_reached(); } +static MemOp cc_op_size(CCOp op) +{ + MemOp size = op & 3; + + assert(op >= CC_OP_FIRST_BWLQ && op <= CC_OP_LAST_BWLQ); + assert(size <= MO_TL); + + return size; +} + static void set_cc_op_1(DisasContext *s, CCOp op, bool dirty) { int dead; @@ -884,7 +894,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) switch (s->cc_op) { case CC_OP_SUBB ... CC_OP_SUBQ: /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */ - size = s->cc_op - CC_OP_SUBB; + size = cc_op_size(s->cc_op); gen_ext_tl(s->cc_srcT, s->cc_srcT, size, false); gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false); return (CCPrepare) { .cond = TCG_COND_LTU, .reg = s->cc_srcT, @@ -892,7 +902,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) case CC_OP_ADDB ... CC_OP_ADDQ: /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ - size = s->cc_op - CC_OP_ADDB; + size = cc_op_size(s->cc_op); gen_ext_tl(cpu_cc_dst, cpu_cc_dst, size, false); gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false); return (CCPrepare) { .cond = TCG_COND_LTU, .reg = cpu_cc_dst, @@ -910,7 +920,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) case CC_OP_SHLB ... CC_OP_SHLQ: /* (CC_SRC >> (DATA_BITS - 1)) & 1 */ - size = s->cc_op - CC_OP_SHLB; + size = cc_op_size(s->cc_op); return gen_prepare_sign_nz(cpu_cc_src, size); case CC_OP_MULB ... CC_OP_MULQ: @@ -918,7 +928,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) .reg = cpu_cc_src }; case CC_OP_BMILGB ... CC_OP_BMILGQ: - size = s->cc_op - CC_OP_BMILGB; + size = cc_op_size(s->cc_op); gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false); return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_src }; @@ -972,10 +982,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg) case CC_OP_POPCNT: return (CCPrepare) { .cond = TCG_COND_NEVER }; default: - { - MemOp size = (s->cc_op - CC_OP_ADDB) & 3; - return gen_prepare_sign_nz(cpu_cc_dst, size); - } + return gen_prepare_sign_nz(cpu_cc_dst, cc_op_size(s->cc_op)); } } @@ -1016,7 +1023,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) return (CCPrepare) { .cond = TCG_COND_ALWAYS }; default: { - MemOp size = (s->cc_op - CC_OP_ADDB) & 3; + MemOp size = cc_op_size(s->cc_op); if (size == MO_TL) { return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_dst }; } else { @@ -1042,7 +1049,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) switch (s->cc_op) { case CC_OP_SUBB ... CC_OP_SUBQ: /* We optimize relational operators for the cmp/jcc case. */ - size = s->cc_op - CC_OP_SUBB; + size = cc_op_size(s->cc_op); switch (jcc_op) { case JCC_BE: gen_ext_tl(s->cc_srcT, s->cc_srcT, size, false); @@ -3176,7 +3183,7 @@ static void disas_insn_old(DisasContext *s, CPUState *cpu, int b) CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the same width. */ tcg_gen_mov_tl(cpu_cc_src, s->tmp4); - set_cc_op(s, ((s->cc_op - CC_OP_MULB) & 3) + CC_OP_SARB); + set_cc_op(s, CC_OP_SARB + cc_op_size(s->cc_op)); break; default: /* Otherwise, generate EFLAGS and replace the C bit. */ diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 38b399783e..e9d5d196ce 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -3106,7 +3106,8 @@ static bool gen_eflags_adcox(DisasContext *s, X86DecodedInsn *decode, bool want_ * bit, we might as well fish CF out of EFLAGS and save a shift. */ if (want_carry && (!need_flags || s->cc_op == CC_OP_SHLB + MO_TL)) { - tcg_gen_shri_tl(decode->cc_dst, cpu_cc_src, (8 << (s->cc_op - CC_OP_SHLB)) - 1); + MemOp size = cc_op_size(s->cc_op); + tcg_gen_shri_tl(decode->cc_dst, cpu_cc_src, (8 << size) - 1); got_cf = true; } gen_mov_eflags(s, decode->cc_src);