From patchwork Wed Jul 24 19:47:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierrick Bouvier X-Patchwork-Id: 814172 Delivered-To: patch@linaro.org Received: by 2002:adf:e641:0:b0:367:895a:4699 with SMTP id b1csp94642wrn; Wed, 24 Jul 2024 12:47:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXsXSvJWMaOKA+hF2U1EClKhVlpHiN8tNhwmNhgmczYxidk/QOAgfzbGbFGtrWykDgF3vetZ+kyuMKGUr9sJPPw X-Google-Smtp-Source: AGHT+IGo4/ThGxKdzYkLztMpWhULteXR7vJaLs/Ejq9u7QZO0xBuoH6OYm+An68D3G+E0MttNcOy X-Received: by 2002:a05:6359:4c9d:b0:19f:2c7e:a226 with SMTP id e5c5f4694b2df-1acf8878d7amr116116955d.5.1721850476009; Wed, 24 Jul 2024 12:47:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721850475; cv=none; d=google.com; s=arc-20160816; b=jKqK12zF7x+262sCEybA0+hxVz1rweF2fCKmwXr4LKen2LscWB8viI/bY0kPLqsMjL KnpBi5649++zH1/jdjd1jpP4NXj2YfZ6KkhgQ+2RoWitw17mlqNPaZ03wLsaAHy1A7pt OVTnrWbZI12KrUkm6keHxcDFJdZdjaK1f7VViXkWVEt3/Y3Iw01WurXlZcoTjFNFN/89 A0bo3NzApg5Wq03zKun0EqM/DNY/t0YNjlN89LdiGzUcykYibpALNLSJQwLQj6CA0JXs q+PrRDrH/a+VdgHuORBC7jW3kBT13LWT8LGD0MBJNVj4z1UFdEOvauUcnG+oCZ5S2AAt XAvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jujw3dcwSHYk44u92QIn+K4fYEBnVKCK000Riefc95g=; fh=xnCpbbVYJFFG+A0G6b4cSDVMgju0ymiCog0e/FTUtiE=; b=retA1dpFhRVPexiMRmv0PBiSv0NbfMXdqnzD74qe39qX1PTbz4Yg7EAz0dFDiriacc 4hB3fo1AR0CQlJXfNco6UHrs8+9KQ5MTUo4fwuc0oFLZ0SVrMvKb7BMJbNc2q48tKcmC 8Ds93xQcSivy7A8MB64wxHAszT5FDN9qd0QbJNexvyivq9tKRbmad27wNQcPB8BlVF/0 ljkTcIjTr2kg+IlbRmHUuikjR0nGMuMsiQyjACB5JKMi+cpyG25mrG3TDbFBX+LePzsm JNOFR+Dehq6np05Le0lKRC1RI6qCk4edjPElUMXYG6FAO0wAn8HPeflyWYBNsp0KukY6 ozfg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jGst0dpy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6b7ac99cdbesi136672856d6.218.2024.07.24.12.47.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jul 2024 12:47:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jGst0dpy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sWhxY-0002Q7-BI; Wed, 24 Jul 2024 15:47:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sWhxT-0002Ms-Em for qemu-devel@nongnu.org; Wed, 24 Jul 2024 15:47:32 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sWhxP-0006Fv-Pd for qemu-devel@nongnu.org; Wed, 24 Jul 2024 15:47:31 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-70d1cbbeeaeso146255b3a.0 for ; Wed, 24 Jul 2024 12:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721850444; x=1722455244; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jujw3dcwSHYk44u92QIn+K4fYEBnVKCK000Riefc95g=; b=jGst0dpygxwIhKSRkM8OYGImXkUvj/tWocM8eK67VNt21SoscV56FY+yt2JKQ2B6+F tJYh6kVX8+e8SYE/ugALGRekzI97MiRwl8ZwmGrgSLPsTrcgl9xPpIYqBnbgRK99oIso 3OBlMyPH8pSmhfjZNFrjrUUul+FJIzTyQil2NBkNvbxNf0JVJzVMuW8t/4kOA6S3US+/ 0c9hC/I8TYjw03al4GXtBsa4T5AsD8WUTCFgWBvz0ZmySi6WDfNhTIdef6IVP9d7xYjX cpkAZzRYRo8mRUHZnGvrkcd6xuBSJ1L1NxjcnCYkybV2DurVeB7KdnUv6nNLcMsVHGgj MeLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721850444; x=1722455244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jujw3dcwSHYk44u92QIn+K4fYEBnVKCK000Riefc95g=; b=EpgvcdHBc99FRqQP50sGt2EaqVthF0zOciA/Ok6DYvxBmk7uMwIjEi+8KrcPNdLw5P dqIpSH7Ywgb7Jlq8JHNQ7Q11H7KxSKQPlUOcovHf3hzH1EANMNa9Qhhys4O1KbpXBQmm /q1NoKjqZTvQaxaSHQ8pILXRxPdI0z3AL57K8aYZYjI2mWJmXSGlkyZmV+KYeWFGS5gq 4dfHXEOQtsT/nFw7nHIudwiz+SsiaP3TM1/wBW89Rji5u45JFmosFWE74RL9R+KBiutg 3iux9WgO5k1WJpkokO04ICNz4RrHgAnvnuoWsGXYt76lW1+5b6VFuLTJKRLtSD3T5Ibj WJ0A== X-Gm-Message-State: AOJu0Yy7OAIJDBDq7UIKKWh3XZHQYlTcFld+FZxqAZfVtpxb9lltgLEP NbcaRnpSOXi43lfYyDB1zv6hvU6BKoNAUO6efT3t4Q/gHrUKDxJaLKWIhVjhFM3Npt1jkDfisyg eTig= X-Received: by 2002:a05:6a00:18a2:b0:70b:20d9:3c2a with SMTP id d2e1a72fcca58-70eaa947c02mr626992b3a.28.1721850444310; Wed, 24 Jul 2024 12:47:24 -0700 (PDT) Received: from linaro.vn.shawcable.net ([2604:3d08:9384:1d00::b861]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70d19c52a62sm6339116b3a.124.2024.07.24.12.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jul 2024 12:47:23 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Alexandre Iooss , Zhao Liu , Mahmoud Mandour , Yanan Wang , Pierrick Bouvier , Eduardo Habkost , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= , Richard Henderson , Marcel Apfelbaum , Xingtao Yao Subject: [PATCH v7 6/6] tests/tcg/multiarch: add test for plugin memory access Date: Wed, 24 Jul 2024 12:47:08 -0700 Message-Id: <20240724194708.1843704-7-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240724194708.1843704-1-pierrick.bouvier@linaro.org> References: <20240724194708.1843704-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add an explicit test to check expected memory values are read/written. 8,16,32 load/store are tested for all arch. 64,128 load/store are tested for aarch64/x64. atomic operations (8,16,32,64) are tested for x64 only. By default, atomic accesses are non atomic if a single cpu is running, so we force creation of a second one by creating a new thread first. load/store helpers code path can't be triggered easily in user mode (no softmmu), so we can't test it here. Output of test-plugin-mem-access.c is the list of expected patterns in plugin output. By reading stdout, we can compare to plugins output and have a multiarch test. Can be run with: make -C build/tests/tcg/$ARCH-linux-user run-plugin-test-plugin-mem-access-with-libmem.so Tested-by: Xingtao Yao Signed-off-by: Pierrick Bouvier --- tests/tcg/multiarch/test-plugin-mem-access.c | 175 ++++++++++++++++++ tests/tcg/multiarch/Makefile.target | 7 + .../tcg/multiarch/check-plugin-mem-access.sh | 30 +++ 3 files changed, 212 insertions(+) create mode 100644 tests/tcg/multiarch/test-plugin-mem-access.c create mode 100755 tests/tcg/multiarch/check-plugin-mem-access.sh diff --git a/tests/tcg/multiarch/test-plugin-mem-access.c b/tests/tcg/multiarch/test-plugin-mem-access.c new file mode 100644 index 00000000000..09d1fa22e35 --- /dev/null +++ b/tests/tcg/multiarch/test-plugin-mem-access.c @@ -0,0 +1,175 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Check if we detect all memory accesses expected using plugin API. + * Used in conjunction with ./check-plugin-mem-access.sh check script. + * Output of this program is the list of patterns expected in plugin output. + * + * 8,16,32 load/store are tested for all arch. + * 64,128 load/store are tested for aarch64/x64. + * atomic operations (8,16,32,64) are tested for x64 only. + */ + +#include +#include +#include +#include + +#if defined(__x86_64__) +#include +#elif defined(__aarch64__) +#include +#endif /* __x86_64__ */ + +static void *data; + +/* ,store_u8,.*,8,store,0xf1 */ +#define PRINT_EXPECTED(function, type, value, action) \ +do { \ + printf(",%s,.*,%d,%s,%s\n", \ + #function, (int) sizeof(type) * 8, action, value); \ +} \ +while (0) + +#define DEFINE_STORE(name, type, value) \ + \ +static void print_expected_store_##name(void) \ +{ \ + PRINT_EXPECTED(store_##name, type, #value, "store"); \ +} \ + \ +static void store_##name(void) \ +{ \ + *((type *)data) = value; \ + print_expected_store_##name(); \ +} + +#define DEFINE_ATOMIC_OP(name, type, value) \ + \ +static void print_expected_atomic_op_##name(void) \ +{ \ + PRINT_EXPECTED(atomic_op_##name, type, "0x0*42", "load"); \ + PRINT_EXPECTED(atomic_op_##name, type, #value, "store"); \ +} \ + \ +static void atomic_op_##name(void) \ +{ \ + *((type *)data) = 0x42; \ + __sync_val_compare_and_swap((type *)data, 0x42, value); \ + print_expected_atomic_op_##name(); \ +} + +#define DEFINE_LOAD(name, type, value) \ + \ +static void print_expected_load_##name(void) \ +{ \ + PRINT_EXPECTED(load_##name, type, #value, "load"); \ +} \ + \ +static void load_##name(void) \ +{ \ + type src = *((type *) data); \ + type dest = src; \ + (void)src, (void)dest; \ + print_expected_load_##name(); \ +} + +DEFINE_STORE(u8, uint8_t, 0xf1) +DEFINE_LOAD(u8, uint8_t, 0xf1) +DEFINE_STORE(u16, uint16_t, 0xf123) +DEFINE_LOAD(u16, uint16_t, 0xf123) +DEFINE_STORE(u32, uint32_t, 0xff112233) +DEFINE_LOAD(u32, uint32_t, 0xff112233) + +#if defined(__x86_64__) || defined(__aarch64__) +DEFINE_STORE(u64, uint64_t, 0xf123456789abcdef) +DEFINE_LOAD(u64, uint64_t, 0xf123456789abcdef) + +static void print_expected_store_u128(void) +{ + PRINT_EXPECTED(store_u128, __int128, + "0xf122334455667788f123456789abcdef", "store"); +} + +static void store_u128(void) +{ +#ifdef __x86_64__ + _mm_store_si128(data, _mm_set_epi32(0xf1223344, 0x55667788, + 0xf1234567, 0x89abcdef)); +#else + const uint32_t init[4] = {0x89abcdef, 0xf1234567, 0x55667788, 0xf1223344}; + uint32x4_t vec = vld1q_u32(init); + vst1q_u32(data, vec); +#endif /* __x86_64__ */ + print_expected_store_u128(); +} + +static void print_expected_load_u128(void) +{ + PRINT_EXPECTED(load_u128, __int128, + "0xf122334455667788f123456789abcdef", "load"); +} + +static void load_u128(void) +{ +#ifdef __x86_64__ + __m128i var = _mm_load_si128(data); +#else + uint32x4_t var = vld1q_u32(data); +#endif + (void) var; + print_expected_load_u128(); +} +#endif /* __x86_64__ || __aarch64__ */ + +#if defined(__x86_64__) +DEFINE_ATOMIC_OP(u8, uint8_t, 0xf1) +DEFINE_ATOMIC_OP(u16, uint16_t, 0xf123) +DEFINE_ATOMIC_OP(u32, uint32_t, 0xff112233) +DEFINE_ATOMIC_OP(u64, uint64_t, 0xf123456789abcdef) +#endif /* __x86_64__ */ + +static void *f(void *p) +{ + return NULL; +} + +int main(void) +{ + /* + * We force creation of a second thread to enable cpu flag CF_PARALLEL. + * This will generate atomic operations when needed. + */ + pthread_t thread; + pthread_create(&thread, NULL, &f, NULL); + pthread_join(thread, NULL); + + /* allocate storage up to 128 bits */ + data = malloc(16); + + store_u8(); + load_u8(); + + store_u16(); + load_u16(); + + store_u32(); + load_u32(); + +#if defined(__x86_64__) || defined(__aarch64__) + store_u64(); + load_u64(); + + store_u128(); + load_u128(); +#endif /* __x86_64__ || __aarch64__ */ + +#if defined(__x86_64__) + atomic_op_u8(); + atomic_op_u16(); + atomic_op_u32(); + atomic_op_u64(); +#endif /* __x86_64__ */ + + free(data); +} diff --git a/tests/tcg/multiarch/Makefile.target b/tests/tcg/multiarch/Makefile.target index 5e3391ec9d2..d90cbd3e521 100644 --- a/tests/tcg/multiarch/Makefile.target +++ b/tests/tcg/multiarch/Makefile.target @@ -170,5 +170,12 @@ run-plugin-semiconsole-with-%: TESTS += semihosting semiconsole endif +# Test plugin memory access instrumentation +run-plugin-test-plugin-mem-access-with-libmem.so: \ + PLUGIN_ARGS=$(COMMA)print-accesses=true +run-plugin-test-plugin-mem-access-with-libmem.so: \ + CHECK_PLUGIN_OUTPUT_COMMAND= \ + $(SRC_PATH)/tests/tcg/multiarch/check-plugin-mem-access.sh + # Update TESTS TESTS += $(MULTIARCH_TESTS) diff --git a/tests/tcg/multiarch/check-plugin-mem-access.sh b/tests/tcg/multiarch/check-plugin-mem-access.sh new file mode 100755 index 00000000000..909606943bb --- /dev/null +++ b/tests/tcg/multiarch/check-plugin-mem-access.sh @@ -0,0 +1,30 @@ +#!/usr/bin/env bash + +set -euo pipefail + +die() +{ + echo "$@" 1>&2 + exit 1 +} + +check() +{ + file=$1 + pattern=$2 + grep "$pattern" "$file" > /dev/null || die "\"$pattern\" not found in $file" +} + +[ $# -eq 1 ] || die "usage: plugin_out_file" + +plugin_out=$1 + +expected() +{ + ./test-plugin-mem-access || + die "running test-plugin-mem-access executable failed" +} + +expected | while read line; do + check "$plugin_out" "$line" +done