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[176.184.54.166]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8d25835551sm401436766b.24.2024.09.09.16.19.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 09 Sep 2024 16:19:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , qemu-s390x@nongnu.org, Thomas Huth , Ilya Leoshkevich , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v2 06/10 2/4] target/s390x: Use deposit to set psw_mask in save_link_info Date: Tue, 10 Sep 2024 01:19:08 +0200 Message-ID: <20240909231910.14428-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240605215739.4758-7-richard.henderson@linaro.org> References: <20240605215739.4758-7-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20240605215739.4758-7-richard.henderson@linaro.org> [PMD: Split patch, part 2/4] Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/tcg/translate.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index faa6d37c8e..53ec817e29 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1417,6 +1417,7 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o) static void save_link_info(DisasContext *s, DisasOps *o) { + TCGv_i64 t1; TCGv_i64 t2; if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) { @@ -1425,14 +1426,17 @@ static void save_link_info(DisasContext *s, DisasOps *o) } gen_op_calc_cc(s); + t1 = tcg_temp_new_i64(); t2 = tcg_temp_new_i64(); + tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); + + /* Shift program mask into place, garbage outside of [27:24]. */ + tcg_gen_shri_i64(t1, psw_mask, 16); + /* Deposit pc to replace garbage bits below program mask. */ gen_psw_addr_disp(s, t2, s->ilen); - tcg_gen_or_i64(o->out, o->out, t2); + tcg_gen_deposit_i64(o->out, t1, t2, 0, 24); tcg_gen_ori_i64(o->out, o->out, (s->ilen / 2) << 30); - tcg_gen_shri_i64(t2, psw_mask, 16); - tcg_gen_andi_i64(t2, t2, 0x0f000000); - tcg_gen_or_i64(o->out, o->out, t2); tcg_gen_extu_i32_i64(t2, cc_op); tcg_gen_shli_i64(t2, t2, 28); tcg_gen_or_i64(o->out, o->out, t2);