From patchwork Sat Oct 5 15:25:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832978 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1256249wra; Sat, 5 Oct 2024 08:28:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUOKUelkxc4R6jv7Oue97yk0AgL/p6RRDPPFU/nXjHPrtBiM1lAghmQsnytOm0oxJ1hNugzyg==@linaro.org X-Google-Smtp-Source: AGHT+IGwGqfLx+QD4AhGyPV0GHOBTQKmWd3KiXFyFVrEVL5dJEog+i1n/3hHfaOR8pRyqOFZjeWO X-Received: by 2002:a05:6214:3f83:b0:6cb:99db:bdbf with SMTP id 6a1803df08f44-6cb9a4e7955mr101407926d6.43.1728142139694; Sat, 05 Oct 2024 08:28:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728142139; cv=none; d=google.com; s=arc-20240605; b=Og8/l/mbOCqZmjSS3DVUExa8T3Th6GLXlQRqkplBUCRjnJpRtSbL06jzqhHZ/302FE KTX/xr/uVinDpTnPtxV3zgenk78gCIIoizesFucF8s2O1Eui98iYxZ4g5O6ShVfDOpeX 10M6RDd3Afd5yfns7jXHy40a+HMPHIRvgvBGwWqK9hRHP5+1hOu2SL8f1rkxSiJFMAZF f1g6XRssnJ1Vb6y8bXVv6TTZH2wX/vjjyCd8AAXlUJmre9CcFZRnKJ6RGw6fC2aQWCUm BgVErQdy0ZSGg4ZuKt/90zYeqHEx4adtARx01rr5um3DaJkz6KvEu5gVje47Yzegl3uT IMfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=E1uh5v8Er5HwrssIP/tcmhd1DyyVCAW+cpRhBaU0frQ=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=UtWOMVmc5f8Zb1tp8k8xpim9yj2J0u2rMdbmKGi7kdMKi3upwmcE3vbG3dMCW1mNYn Z/XZUWTrYG5QJ6peZgSOraBfYfqBQdxg8XN36eFxmYHzOtechOLb6f19dSjzbyifIx78 W1Xz/0l7bFTFQd9IyPA1L7yYUN5+jz7IiLy/tMr3L+Umv5HyOHCq4HDbFY9j8Mitd/rO tQR1WZLjuZAW8aAWYmNFtCpvhB7FglCKyugnN2sG/ASJX/Fhp436otOQj9pcRwKENqPe TS/VpTIICaoDqYlQeXStgEqe4xAzmNox0aJzCSGBUgxy/KoWxKw56R5ZPwnqd5frv5TE R95g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XSf6isPk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6cba47722cbsi22643176d6.408.2024.10.05.08.28.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 05 Oct 2024 08:28:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XSf6isPk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sx6fh-0002Bn-W7; Sat, 05 Oct 2024 11:26:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sx6fZ-000268-Lv for qemu-devel@nongnu.org; Sat, 05 Oct 2024 11:26:11 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sx6fW-0002OT-Od for qemu-devel@nongnu.org; Sat, 05 Oct 2024 11:26:09 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-20b833f9b35so26761655ad.2 for ; Sat, 05 Oct 2024 08:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728141965; x=1728746765; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E1uh5v8Er5HwrssIP/tcmhd1DyyVCAW+cpRhBaU0frQ=; b=XSf6isPkETO/Z+QHvF5QsoGZKhS3bQ5aJYcxrXaEPv1JOvpW5a1IciamZcKUBI+ITX x6B9vo2otJVBz3tRUo+MgdQyVEM0LepWBERaiClL/W3RQiEF7Bgl4tB4ohMMRcFYC850 L5rYwgX5320OWuu81ez6Q+byKnHi3gYO8b7AruPUMmeDmuLkqHg9gLRaAxWkEC7B5Fm1 VrA4m9PrqztE9zbYXF+dLxAianCY/5ov+267WnbaicuJ4t6onV9hrejx2ZOXZgs+XxX5 3dw+78iZJrL2VxxgdwpT9O4Kcqgbe1h7PAG5swcfL0CH62VPegoZjMRAauy81Ngil+PO LJiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728141965; x=1728746765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E1uh5v8Er5HwrssIP/tcmhd1DyyVCAW+cpRhBaU0frQ=; b=PUf22U3S1Cs50XySNAJ4Yuwlf9fFqDXlKa4ZzvlNk1hbKSaQk+BeRiSpKdxKFa3jkt MktkYj3EVpxtyPHj4GbIFy/ta0bqHKgwptim9maLoSGbLl/a9TEEW/uhb7Ge6O7HAoIw 5IMWGIXR3f6u3Ipzm1T93uvk/wx2k4A8Ld2ofdntgHyPPwuMA5Dglo5PreYGrUxfoNgp FxbnhcOKshl/wDsuGZXHFYWMuwixO0yY3fXaJil3er+fF6BtCKgrFdUbUjNzYqRsKCFg B8UwBc3Vc8tH3VA9dpyqSe59mb3DjMOFOsk5Y0HQUH4cY5OAGnlwWi5TYBq8Cq+Ad3o6 4cMQ== X-Gm-Message-State: AOJu0Yz0CcR8ROt1ssOiEHsf7W9lJN9WcRy7WcXZZqST3RucuJRsr7jZ dwdNYPj2M99oExPi29vtkqMfCtr/vgLePunLyx2tFYbY+2snASZZInGYFcE2jaB13Xiw498tkD9 A X-Received: by 2002:a17:903:2307:b0:20b:9088:6545 with SMTP id d9443c01a7336-20bfe95dbcfmr96932395ad.46.1728141965422; Sat, 05 Oct 2024 08:26:05 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 13/20] target/arm: Pass MemOp to get_phys_addr Date: Sat, 5 Oct 2024 08:25:44 -0700 Message-ID: <20241005152551.307923-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Zero is the safe do-nothing value for callers to use. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 3 ++- target/arm/ptw.c | 2 +- target/arm/tcg/m_helper.c | 8 ++++---- target/arm/tcg/tlb_helper.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1e5da81ce9..2b16579fa5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1432,6 +1432,7 @@ typedef struct GetPhysAddrResult { * @env: CPUARMState * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute + * @memop: memory operation feeding this access, or 0 for none * @mmu_idx: MMU index indicating required translation regime * @result: set on translation success. * @fi: set to fault info if the translation fails @@ -1450,7 +1451,7 @@ typedef struct GetPhysAddrResult { * value. */ bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 659855133c..373095a339 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3572,7 +3572,7 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, } bool get_phys_addr(CPUARMState *env, vaddr address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { S1Translate ptw = { diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 23d7f73035..f7354f3c6e 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -222,7 +222,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, int exc; bool exc_secure; - if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_STORE, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { if (mode == STACK_LAZYFP) { @@ -311,7 +311,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, bool exc_secure; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -2009,7 +2009,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, "...really SecureFault with SFSR.INVEP\n"); return false; } - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_INST_FETCH, 0, mmu_idx, &res, &fi)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); @@ -2045,7 +2045,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, ARMMMUFaultInfo fi = {}; uint32_t value; - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type == ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 885bf4ec14..1d8b7bcaa2 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -344,7 +344,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * return false. Otherwise populate fsr with ARM DFSR/IFSR fault * register format, and signal the fault. */ - ret = get_phys_addr(&cpu->env, address, access_type, + ret = get_phys_addr(&cpu->env, address, access_type, 0, core_to_arm_mmu_idx(&cpu->env, mmu_idx), &res, fi); if (likely(!ret)) {