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Tue, 26 Nov 2024 05:16:31 -0800 (PST) Received: from localhost.localdomain ([176.176.143.205]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbee043sm13335835f8f.104.2024.11.26.05.16.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 26 Nov 2024 05:16:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang Subject: [PATCH 07/13] target/mips: Introduce gen_load_gpr_i32() Date: Tue, 26 Nov 2024 14:15:39 +0100 Message-ID: <20241126131546.66145-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126131546.66145-1-philmd@linaro.org> References: <20241126131546.66145-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Similarly to the gen_load_gpr_tl() helper which loads a target-wide TCG register from the CPU generic purpose registers, add a helper to load 32-bit TCG register. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 1 + target/mips/tcg/translate.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 9517e18eef9..e15d631ad2a 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -156,6 +156,7 @@ void gen_base_offset_addr_tl(DisasContext *ctx, TCGv addr, int base, int offset) void gen_move_low32_tl(TCGv ret, TCGv_i64 arg); void gen_move_high32_tl(TCGv ret, TCGv_i64 arg); void gen_load_gpr_tl(TCGv t, int reg); +void gen_load_gpr_i32(TCGv_i32 t, int reg); void gen_store_gpr_tl(TCGv t, int reg); #if defined(TARGET_MIPS64) void gen_load_gpr_hi(TCGv_i64 t, int reg); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index ad688b9b23d..d7c83c863d5 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1198,6 +1198,16 @@ void gen_load_gpr_tl(TCGv t, int reg) } } +void gen_load_gpr_i32(TCGv_i32 t, int reg) +{ + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); + if (reg == 0) { + tcg_gen_movi_i32(t, 0); + } else { + tcg_gen_trunc_tl_i32(t, cpu_gpr[reg]); + } +} + void gen_store_gpr_tl(TCGv t, int reg) { assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr));