diff mbox series

[v3,04/16] target/mips: Call translator_ld() in translate_insn() callees

Message ID 20241126140003.74871-5-philmd@linaro.org
State New
Headers show
Series target/mips: Convert nanoMIPS LSA opcode to decodetree | expand

Commit Message

Philippe Mathieu-Daudé Nov. 26, 2024, 1:59 p.m. UTC 
Historically we were only calling decode_opc() from the MIPS
translate_insn() handler. Then variable instruction length
ISAs were added, we kept using the same pattern but call
yet more translator_ld() in the callees when necessary.

This is cumbersome and bug prone, so better move all
translator_ld() calls to the callees where it is more
logical.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.c               |  6 ++----
 target/mips/tcg/micromips_translate.c.inc |  3 +++
 target/mips/tcg/mips16e_translate.c.inc   |  5 +++--
 target/mips/tcg/nanomips_translate.c.inc  | 12 +++++++++---
 4 files changed, 17 insertions(+), 9 deletions(-)

Comments

Richard Henderson Nov. 26, 2024, 4:03 p.m. UTC | #1 
On 11/26/24 07:59, Philippe Mathieu-Daudé wrote:
> Historically we were only calling decode_opc() from the MIPS
> translate_insn() handler. Then variable instruction length
> ISAs were added, we kept using the same pattern but call
> yet more translator_ld() in the callees when necessary.
> 
> This is cumbersome and bug prone, so better move all
> translator_ld() calls to the callees where it is more
> logical.
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   target/mips/tcg/translate.c               |  6 ++----
>   target/mips/tcg/micromips_translate.c.inc |  3 +++
>   target/mips/tcg/mips16e_translate.c.inc   |  5 +++--
>   target/mips/tcg/nanomips_translate.c.inc  | 12 +++++++++---
>   4 files changed, 17 insertions(+), 9 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6fd5462a24f..0495fbe1dc6 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15000,6 +15000,8 @@  static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         gen_set_label(l1);
     }
 
+    ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
+
     /* Transition to the auto-generated decoder.  */
 
     /* Vendor specific extensions */
@@ -15120,17 +15122,13 @@  static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
 
     is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
     if (ctx->insn_flags & ISA_NANOMIPS32) {
-        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = decode_isa_nanomips(env, ctx);
     } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
-        ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = 4;
         decode_opc(env, ctx);
     } else if (ctx->insn_flags & ASE_MICROMIPS) {
-        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = decode_isa_micromips(env, ctx);
     } else if (ctx->insn_flags & ASE_MIPS16) {
-        ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
         insn_bytes = decode_ase_mips16e(env, ctx);
     } else {
         gen_reserved_instruction(ctx);
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index c479bec1081..98a00125520 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -2973,6 +2973,7 @@  static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
 
 static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx)
 {
+    uint32_t opcode;
     uint32_t op;
 
     /* make sure instructions are on a halfword boundary */
@@ -2982,6 +2983,8 @@  static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx)
         return 2;
     }
 
+    opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
+    ctx->opcode = opcode;
     op = (ctx->opcode >> 10) & 0x3f;
     /* Enforce properly-sized instructions in a delay slot */
     if (ctx->hflags & MIPS_HFLAG_BDS_STRICT) {
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index a9af8f1e74a..defef3ce559 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -453,11 +453,9 @@  static void decode_i64_mips16(DisasContext *ctx,
 
 static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
 {
-    int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
     int op, rx, ry, funct, sa;
     int16_t imm, offset;
 
-    ctx->opcode = (ctx->opcode << 16) | extend;
     op = (ctx->opcode >> 11) & 0x1f;
     sa = (ctx->opcode >> 22) & 0x1f;
     funct = (ctx->opcode >> 8) & 0x7;
@@ -658,6 +656,7 @@  static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
     int funct;
     int n_bytes;
 
+    ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
     op = (ctx->opcode >> 11) & 0x1f;
     sa = (ctx->opcode >> 2) & 0x7;
     sa = sa == 0 ? 8 : sa;
@@ -1103,6 +1102,8 @@  static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case M16_OPC_EXTEND:
+        ctx->opcode <<= 16;
+        ctx->opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
         decode_extended_mips16_opc(env, ctx);
         n_bytes = 4;
         break;
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 1e274143bbd..6ee0c4fca3b 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -4467,10 +4467,11 @@  static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
 
 static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
 {
+    uint64_t opcode;
     uint32_t op;
-    int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
-    int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
-    int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
+    int rt;
+    int rs;
+    int rd;
     int offset;
     int imm;
 
@@ -4482,6 +4483,11 @@  static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
         return 2;
     }
 
+    opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
+    ctx->opcode = opcode;
+    rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
+    rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
+    rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
     op = extract32(ctx->opcode, 10, 6);
     switch (op) {
     case NM_P16_MV: