From patchwork Wed Dec 11 16:30:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 849243 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:2c4:b0:385:e875:8a9e with SMTP id o4csp423472wry; Wed, 11 Dec 2024 08:38:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXpTusFVOr+cfb+sgv5hUwWhKZ36gXrRq/2+Fq8ihAVUyCxgy0Ej1nsT6FiIRCGGvPtjkgxhQ==@linaro.org X-Google-Smtp-Source: AGHT+IEU+TgPyTrU9Pmc7h984u+FBk6ayvfbZHceDfZayTrR+/fdCuuWlRhpxBYv+sr6sEaNj/9L X-Received: by 2002:a05:6102:2ad4:b0:4b0:ccec:c9de with SMTP id ada2fe7eead31-4b2478dd908mr100569137.24.1733935137971; Wed, 11 Dec 2024 08:38:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733935137; cv=none; d=google.com; s=arc-20240605; b=j/g1uONuJu+KKT5mGH+QLDAQeU+ZKNItbI38WM54aWzjzAY1XNyMe9PtpzJGlybNpu QD2+t0JFim2yqVFZcESPax+T46maPikCM+2pxuxh7n/lgsIuZ6i0LwIaWmE5laGPR9eH JEAz1sZNkQ0JNTeElOXK7XL9WW+4CBzBgtSmd6lGkxmqUEh4Ow2vsV7gY41rXkTBSJZ6 VhGwmRka7x80giJk/KaFWE0zDCs7NYv+G0ngsVafwTIZMy40OiwyXw3P2QxJn24DCwVP VUDgdbDpSA+S0myy9vdL0h9/bvEDbjm33iFsFTdsBwGEvxfxsGPlfTiBwS6U0On2QZ4F vaQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fmnG9zV0F6eG9aGozAfqS/Ir0uR/PDhoKeXguNvBnYQ=; fh=ZhBia3nL9o1nuf7SbgdYn/0pDmAeja6gisyWXi2cqYE=; b=kGmbqT8uQuqJGCjcX0Zw5TlX4BTPNKt21iVm33KrL3sCNTQmEtJKi4mQuaQr/QbmcK X+zJss0smhKF8/S4mm0i15R16ezuZBKe/UELwu+7NWKVBi52Z0NVkAXGh9Koqm8qPGSF dkyErBcK1OccBFmlIt9Fu60bLXagHKIxk+sG7ukz6FqwZi0JF1jViFQAb4JHmLQhbZ5Q AHJqZvQG161wGQha8tGQKG1eyReCwl+leulhwBc2yv2STG2CoLZTDoUn3f81P8B0D6JR xEyGOqb7Fpb7eGj8QGaFJpxqmGW7WKNXdQIYt3UoxxUhVWsY5EIi5YmnxT13cqvKfRNJ txKA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aIma41Nd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4afee1911a4si1824132137.388.2024.12.11.08.38.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 11 Dec 2024 08:38:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aIma41Nd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPhq-0001an-SX; Wed, 11 Dec 2024 11:36:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPhj-00017b-8G for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:36:51 -0500 Received: from mail-qv1-xf30.google.com ([2607:f8b0:4864:20::f30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPhe-0002I5-Ua for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:36:49 -0500 Received: by mail-qv1-xf30.google.com with SMTP id 6a1803df08f44-6d8edad9932so39772606d6.0 for ; Wed, 11 Dec 2024 08:36:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733935006; x=1734539806; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fmnG9zV0F6eG9aGozAfqS/Ir0uR/PDhoKeXguNvBnYQ=; b=aIma41Ndsti+hWY0C2DhLuq0j9eh8aQB0zsC1+Gw7+0yc8Q/HLQ6sz0IRdZjAX94U4 q0kMxzAO5CKI3F3C/YWG98wbpwILTv2iQzFImDGasUuEu0eKkCIJg7mSzTEZb3CDS8sw SD5RPMRjZFypQ8HsMy0mVyc/wGlkJlyduDJ7c00WUMzDRnk1sfLnkgCyDkrvSFxnqztH CvmdyJgOyzcNZpov85SPAcWTPTMb31ulZjqb//v6pc3OClQxU5Tv6PS/E+s1cqlwyWMO vFxRGXiJIOeU+uPw7OwvYsM78mclOJYOXFt+vN25x2ogyR1OyNOtCiR+Un3594LT/4P8 csYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733935006; x=1734539806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fmnG9zV0F6eG9aGozAfqS/Ir0uR/PDhoKeXguNvBnYQ=; b=T7UXYBxwgQiR5/MfQ0fpwmfj0SKEZc4JkgEy8xZSlCci99BmCms7lA1/Z1m/erRp3G /3HFVcNh0UT6ECqdDyHweuRzI7dgSdEbUqeVzrWBxTHAu0/8YpSvNbrGrKZzD6zEd1MO pNMmNXXFpFHrjgYxVnhQrjhVoBEerE0YeddtS30/zmAEGfrBt/1Sz/1rDQOT5WdTxehS UXsmcw8NNnEk73zjGBsi/JUf1grcxi80SJTpu14hucfZx/EIl0H5FLR3aQ7q87e4gTFK 6cGeHIaWaRO0C2oOUarXEeBEemvizeJ/qo5QO5g9mE5SNDcpGsUbq4ELf6h7Iw/lYju4 wpNQ== X-Gm-Message-State: AOJu0YyrhSuxNKrIK2snIyeGvwGllVgvt8b7IhL922aW76fE+uVPle9o 19LZu6Om3kUEWUeWgZf1Re7MWMLj3TD/sIe7jdPEkuY1AWQWDaGqX4syQ+r2GEA4XfE9N+DBqcv jRC14mLyJ X-Gm-Gg: ASbGncuH84/BgqaVYbhzM70kNJfCt5DHeeSzgy/75ER5+6k34XpA6JgGvVDiMiSh8Vz H/fGxJCi72q3c3+GuJdGCaej8gFMc2nN5iVUaGPvRk5EdfCgYUtlhoDlGE3UQ6QhmzpKfkYlhGq p09t4BxyyJadykDEMptn8jzkUXEGWN6TlvdvuLj3O7JK7WjhCuQvz/PCe0N4y6KD1tekHPmpx6Q s6iRSNkfEoQraIIiuEsdFxdhQjRYtc7tmWA4Nlgrv+9w+/4JYXrcAOhwJJheTOC X-Received: by 2002:ad4:518e:0:b0:6da:dbf0:962a with SMTP id 6a1803df08f44-6dadbf0985dmr29519856d6.9.1733935005974; Wed, 11 Dec 2024 08:36:45 -0800 (PST) Received: from stoup.. ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6d8da675214sm71856276d6.11.2024.12.11.08.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:36:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 60/69] target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree Date: Wed, 11 Dec 2024 10:30:27 -0600 Message-ID: <20241211163036.2297116-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241211163036.2297116-1-richard.henderson@linaro.org> References: <20241211163036.2297116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f30; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove disas_simd_scalar_shift_imm as these were the last insns decoded by that function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 47 ---------------------------------- target/arm/tcg/a64.decode | 8 ++++++ 2 files changed, 8 insertions(+), 47 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6e9d040ebf..08f24908a4 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -9531,52 +9531,6 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, gen_restore_rmode(tcg_rmode, tcg_fpstatus); } -/* AdvSIMD scalar shift by immediate - * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 - * +-----+---+-------------+------+------+--------+---+------+------+ - * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | - * +-----+---+-------------+------+------+--------+---+------+------+ - * - * This is the scalar version so it works on a fixed sized registers - */ -static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) -{ - int rd = extract32(insn, 0, 5); - int rn = extract32(insn, 5, 5); - int opcode = extract32(insn, 11, 5); - int immb = extract32(insn, 16, 3); - int immh = extract32(insn, 19, 4); - bool is_u = extract32(insn, 29, 1); - - if (immh == 0) { - unallocated_encoding(s); - return; - } - - switch (opcode) { - case 0x1c: /* SCVTF, UCVTF */ - handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, - opcode, rn, rd); - break; - default: - case 0x00: /* SSHR / USHR */ - case 0x02: /* SSRA / USRA */ - case 0x04: /* SRSHR / URSHR */ - case 0x06: /* SRSRA / URSRA */ - case 0x08: /* SRI */ - case 0x0a: /* SHL / SLI */ - case 0x0c: /* SQSHLU */ - case 0x0e: /* SQSHL, UQSHL */ - case 0x10: /* SQSHRUN */ - case 0x11: /* SQRSHRUN */ - case 0x12: /* SQSHRN, UQSHRN */ - case 0x13: /* SQRSHRN, UQRSHRN */ - case 0x1f: /* FCVTZS, FCVTZU */ - unallocated_encoding(s); - break; - } -} - static void handle_2misc_64(DisasContext *s, int opcode, bool u, TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) @@ -10476,7 +10430,6 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, - { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 146500d9c4..30e1834d99 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1699,6 +1699,14 @@ FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd @fcvt_fixed_d .... .... . 1 ...... ...... rn:5 rd:5 \ &fcvt sf=0 esz=3 shift=%fcvt_f_sh_d +SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_h +SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_s +SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_d + +UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_h +UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_s +UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_d + FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_h FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_s FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_d