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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4366127c4bbsm357117475e9.32.2024.12.30.07.39.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Dec 2024 07:39:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stafford Horne , Zhao Liu , qemu-ppc@nongnu.org, Yanan Wang , Eduardo Habkost , Song Gao , Bernhard Beschow , qemu-arm@nongnu.org, Marcel Apfelbaum , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 3/3] target/cpus: Remove pointless re-assignment of CPUState::halted Date: Mon, 30 Dec 2024 16:39:29 +0100 Message-ID: <20241230153929.87137-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230153929.87137-1-philmd@linaro.org> References: <20241230153929.87137-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The CPUState::halted field is always re-initialized in cpu_common_reset_hold(), itself called by cpu_reset(). No need to have targets manually initializing it. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Bernhard Beschow --- hw/misc/mips_cpc.c | 1 - hw/ppc/e500.c | 1 - target/arm/arm-powerctl.c | 2 -- target/hppa/cpu.c | 1 - 4 files changed, 5 deletions(-) diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c index 772b8c0017d..4ec8226c416 100644 --- a/hw/misc/mips_cpc.c +++ b/hw/misc/mips_cpc.c @@ -38,7 +38,6 @@ static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data) MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr; cpu_reset(cs); - cs->halted = 0; cpc->vp_running |= 1ULL << cs->cpu_index; } diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 4551157c011..8b90b5b2448 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -785,7 +785,6 @@ static void ppce500_cpu_reset(void *opaque) cpu_reset(cs); /* Set initial guest state. */ - cs->halted = 0; env->gpr[1] = (16 * MiB) - 8; env->gpr[3] = bi->dt_base; env->gpr[4] = 0; diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 20c70c7d6bb..8e948171c7c 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -67,7 +67,6 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, /* Initialize the cpu we are turning on */ cpu_reset(target_cpu_state); arm_emulate_firmware_reset(target_cpu_state, info->target_el); - target_cpu_state->halted = 0; /* We check if the started CPU is now at the correct level */ assert(info->target_el == arm_current_el(&target_cpu->env)); @@ -194,7 +193,6 @@ static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state, /* Initialize the cpu we are turning on */ cpu_reset(target_cpu_state); - target_cpu_state->halted = 0; /* Finally set the power status */ assert(bql_locked()); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9b355bfe902..b4092037888 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,7 +203,6 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) if (scc->parent_phases.hold) { scc->parent_phases.hold(obj, type); } - cs->halted = 0; cpu_set_pc(cs, 0xf0000004); memset(env, 0, offsetof(CPUHPPAState, end_reset_fields));