From patchwork Thu Feb 6 13:10:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862498 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp118391wrv; Thu, 6 Feb 2025 05:12:04 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWFC5HhawRd6iku189jKTl2Z1PfERI1XlpwGTeRG/bbnc+bd+UNEJ+pD5t4Ma2s7xc8l70/9w==@linaro.org X-Google-Smtp-Source: AGHT+IEu2roZl5PHWR07jFWN1mfOI7mjVOhhSVVJovlWCa4n8y3VcaOiR3mpbYGGjYcvPLvfuxg+ X-Received: by 2002:a05:6214:418a:b0:6e2:4ad7:24c8 with SMTP id 6a1803df08f44-6e42fb23793mr88962226d6.2.1738847524508; Thu, 06 Feb 2025 05:12:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738847524; cv=none; d=google.com; s=arc-20240605; b=JMFy1ydbx90vRBB787I2T87G0GY3Bow66+/4ynB8Ire677dlZfFwFs9iOZQxlZt7+1 1C4WT6dmSBFwmvfsAG0AKGzA5id3tC8JtdKORJGYXEie3JQhDwv6y4zHeHZeNU9wiWNs 0yYIfG+CPRBqjdUPWDZiLO3jBjYtHT+SgJiJPe5R1JKUoVgX9WpJc3HY0zN0D2n7Vpos oi43mFStv+PLUeR0v1dLBnM+74P//iHL36uosH204koWm2ea18VDQz4X2GIZ13HShkC7 Q/a67mzPqS2wVkEJjBR02LzMly5wu1pNNEPRNiI1sfcB0lU8WNmmGFy2AChpTfrwFGF9 nZNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4b8oiIF0V/wXvMZ/KNd/Z66f59JylUbcAbl8fgf5Kk8=; fh=7NsVx5R+L140HvZ0es4udPXCD2KdHoHcZm3kdyNBbE4=; b=IFOfruErEHIVM0+1OeHNEbqgkxwSBCSodr8vfEnipTd6YedWbYkhDdBManmTZV0j0A 5z1BYwr+DBDvaX8GUyH3EvfEUfv1LJTsl03CLUcVJ2C+CBPVwvLbv7ZP5EkWrpNz1DY9 TtPg9d+Hr1u7bAsiv67aBmeFCPX+gZvlIrWWxbw0pDRLJl05lbAMYvrCWTp3cUmo2n2D Fzg1U+O/MNLMmrrJtCcw2hu+qWDG3Gr3tBpINt1a4QSIjhwGWjXFFWM6LK/yWkO3aDw8 yOYWH/Mwunt924hIQlqAjEAhKUs2os6qXFs6C+kRjKl6T2mKs8sGxwwmBojvMyyKdBrZ E6yw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mjYRV3Y6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6e43ba2c329si11792146d6.7.2025.02.06.05.12.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Feb 2025 05:12:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mjYRV3Y6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg1fB-00054X-C9; Thu, 06 Feb 2025 08:11:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg1f4-000525-Bg for qemu-devel@nongnu.org; Thu, 06 Feb 2025 08:11:18 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg1f2-00083W-Md for qemu-devel@nongnu.org; Thu, 06 Feb 2025 08:11:18 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-436a03197b2so5841905e9.2 for ; Thu, 06 Feb 2025 05:11:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738847475; x=1739452275; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4b8oiIF0V/wXvMZ/KNd/Z66f59JylUbcAbl8fgf5Kk8=; b=mjYRV3Y6lnFjkafNBX8KR92OKIZKPC/yzeO8SE0SZ2sbIUzfoI7Z/K0SwWMLIE/5D8 mc13ctKCVkB2Y+HEo3xZyXne0FOMGF9UqielHUEeIup8g2EpjubPigThNN2Z20cjbd8H WOT1ehO8XrYpZFcK4IKXe1sEaFGhTkUw8uRwRKhzxdy3bkXsoNZTl1yxb4wzVSIspSus XMM9xkkPe4K1vjddFwyQ4Sab5qjgwbqSg7iuoi76nLQB75Hoft4q72ZyogdIQroAsFQJ Fx9w3+alZmLpQrGr3R24rjUeG/tiJiyCQJQ+f7VcXotbrYHEtOfPU0QrU5IorM3YWSMF heVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738847475; x=1739452275; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4b8oiIF0V/wXvMZ/KNd/Z66f59JylUbcAbl8fgf5Kk8=; b=QcNREhfOKwDI/fVIx24liY77e1e6KU6QaBrAM+32iW/MWMSX8qrPQGPmDF0yf+3LQu lPq2uh5zhi6oSoh0YcruP/sCXBJ8AGtkovBPbWbcHMv3UjpeMDMxMR2DRsGvKgFB84Mp TbLxdkNEe8wo3giGbzhPR+tdy2AocI2WtEdSGmX7vXvVui6TX5NtGHth/XxUjAfA3XAX 9wHiqiNT9tqZWAmQ/sR5UXHpN3gaoxvfKKgD8TM+0xh+xUqdcmnU+EOcEqJaQ7oPTc/V fYnh6Ruyx6O2FTaXkgzlb1FHBdXon/Ds2kDJm1EiyqojWpbzrUFnVAqT+NLAS3TPK2cN ZbSA== X-Gm-Message-State: AOJu0Ywyxz+RBKeTTWeXavgeXrYrxf1FxMsBC9Ph3QUNIrFyGgD4JeU8 bXm0tW2UFjdyndui5OZj7EFoHSK+pb30kjDS/y+S+s1AgNAhnDgdZykBN0uChVxN+VWaJEfZ+hv JDic= X-Gm-Gg: ASbGncuWd0zxMgZof9mTjLT5lmOx5ZMzfexL5pXSTkUR4T0gMdIKMNnzsysI3cLlEhN PGocb9R5iCkU7OIyI0o7TnYqXEK7YI6RWJmHEKg/N7bvSyUVGNtxAzGuQF63E851XYQrb+cMLXu jmMjmYaSny8h/PsiKESZuvtqdNDzy081U0XNCIF5bSFzqaFcPUgHWawAgT9rY9SEwEoZ+2fVTio aiJIBqN03F3djeLDhFxGdh2DhW65sJfBTHWnZmetUBx0Z8OT8OzXYoSS+sHhQQ8fnSaAM250V9Q VB+hc5tF0ajGHxy4xhVqr3yRimPAiljUgRhQ1R8J8JS7SE6aMfmGZSB5q1G2vIfnCw== X-Received: by 2002:a5d:64ab:0:b0:386:4a16:dad7 with SMTP id ffacd0b85a97d-38db48867c7mr5008176f8f.10.1738847474803; Thu, 06 Feb 2025 05:11:14 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d93379fsm56516865e9.5.2025.02.06.05.11.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 05:11:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Anton Johansson , Jason Wang , Paolo Bonzini , Alistair Francis , Thomas Huth , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v5 04/16] hw/char/xilinx_uartlite: Make device endianness configurable Date: Thu, 6 Feb 2025 14:10:40 +0100 Message-ID: <20250206131052.30207-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206131052.30207-1-philmd@linaro.org> References: <20250206131052.30207-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/char/xilinx_uartlite.c | 27 ++++++++++++++---------- hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 56955e0d74a..948da4263b9 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -57,6 +57,7 @@ struct XilinxUARTLite { SysBusDevice parent_obj; + bool little_endian_model; MemoryRegion mmio; CharBackend chr; qemu_irq irq; @@ -166,17 +167,21 @@ uart_write(void *opaque, hwaddr addr, uart_update_irq(s); } -static const MemoryRegionOps uart_ops = { - .read = uart_read, - .write = uart_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4 - } +static const MemoryRegionOps uart_ops[2] = { + [0 ... 1] = { + .read = uart_read, + .write = uart_write, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, + }, + [0].endianness = DEVICE_BIG_ENDIAN, + [1].endianness = DEVICE_LITTLE_ENDIAN, }; static const Property xilinx_uartlite_properties[] = { + DEFINE_PROP_BOOL("little-endian", XilinxUARTLite, little_endian_model, true), DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), }; @@ -214,6 +219,9 @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp) { XilinxUARTLite *s = XILINX_UARTLITE(dev); + memory_region_init_io(&s->mmio, OBJECT(dev), + &uart_ops[s->little_endian_model], + s, "xlnx.xps-uartlite", R_MAX * 4); qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, NULL, s, NULL, true); } @@ -223,9 +231,6 @@ static void xilinx_uartlite_init(Object *obj) XilinxUARTLite *s = XILINX_UARTLITE(obj); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, &uart_ops, s, - "xlnx.xps-uartlite", R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 9d4316b4036..96aed4ed1a3 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -107,6 +107,7 @@ petalogix_s3adsp1800_init(MachineState *machine) } dev = qdev_new(TYPE_XILINX_UARTLITE); + qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);