From patchwork Thu Feb 6 18:18:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 862527 Delivered-To: patch@linaro.org Received: by 2002:a5d:51d2:0:b0:385:e875:8a9e with SMTP id n18csp247199wrv; Thu, 6 Feb 2025 10:20:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXhO6DF0TPELZSELrTaDtXZFdABCtzcHZm3ufLpLfaIVW6Wy2NIpDf4rV/bNGMh5o1MWRdBcA==@linaro.org X-Google-Smtp-Source: AGHT+IEo5TjNXR5+7FF1j/c6hCw+hFmn7cDaZyYE2W6wlgzLvg6U0eIJ/sTatc1dXFpb+FEBtNFO X-Received: by 2002:a05:620a:2616:b0:7b7:28c:dcd9 with SMTP id af79cd13be357-7c047bc73c5mr20029085a.29.1738866052929; Thu, 06 Feb 2025 10:20:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1738866052; cv=none; d=google.com; s=arc-20240605; b=JsSOqi8C5PxtScMnW3X98GTD+4De6BxxDPJqe24CT7km5MXIfqFPf0a4abbYpjtQv+ vb1lR5hmmczUYBczIc75Esmgsg6o9FbOjLBsXBlbFqqBd/DhRtthiOnf/HTTB1HgIr+O 1WiiikB6LRLFDl3T9/EnWt1D21TcwTpfE1hvqm3r+t3Hk3HPkWReafEehbZR1bK/DloM dUcMICH7ust2ZRzAD42EqWxoE7rigEMlP9lyLI4pzfKq33rMf3KtUxPltpRFlGflHiT8 N19MLg9cYtXMdU2NYnk3rucjvGkr6CToK05abCir4UO1n2Z+o249CecEQGej0SM2nWGh o//Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FJl7/XCq/mOYxrX7g6HKZEwMAdetJgh4DocsCwIosNE=; fh=UeiOjk+QPriWQC1kiCEXntK9CMGFOW0Fm2CbXDVlLTw=; b=GYjQ4mrE9/bjSWtPcBoMH1e3LJwYFlBZlf8baNa/vOcNg/q/+T0u6DhD8I4fvi8HMv wnKCni3z71Iwv2bCTBSxxKTmfn4ZQKDYxlJXgRg2BPSE05dvTZAoJFH8r5Uzd8KOfup2 ugq9g7YPUymlUv+oP7TPmg2pnBJTzF3xIr/QNLwT1BdMq71aYs7LOPhR48BW/cpNKGda AyaK7frnuZq9EkSHKzc+mw9HHziUgu2HnP5EPwXUakB5Ze4ICe93JKnYU7NfWRDaObsc loVjOZf61xhvHbny/tkr0wjO1e9rKZp/dBGikXyQMlSCd/HxIDrYjnUzGUxLnaTmZLwT 909A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lAde4DnB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c041eb4ffbsi164016285a.372.2025.02.06.10.20.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Feb 2025 10:20:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lAde4DnB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg6Sg-0007e2-9a; Thu, 06 Feb 2025 13:18:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg6Sb-0007bx-Ez for qemu-devel@nongnu.org; Thu, 06 Feb 2025 13:18:45 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg6SZ-0006oX-9C for qemu-devel@nongnu.org; Thu, 06 Feb 2025 13:18:45 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-436249df846so8657445e9.3 for ; Thu, 06 Feb 2025 10:18:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738865921; x=1739470721; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FJl7/XCq/mOYxrX7g6HKZEwMAdetJgh4DocsCwIosNE=; b=lAde4DnB0uWJJXxZfn03EkrEA80KRWSlSVEr6cFP9UPJ024TjzCEc7GmAbTIUng1Np C1E20ILsmX6iKkNZGatVhBfkpsMst/nQa3eAK5Ie8ZOg3r7GEGTApL2sJ/7aMuHjk+Ir pQf21fmsn24lQxdYlh6mH6qGcmeYL+1idf5A4/ZWt6KAXlypCdqlwXxnOKxc/IZK/9hT J9VfJ4YGLhccyAF+fGKAfxYviGNFp+4n2fFSSJIedm5ddlhA0GOPi1RwFRqCNVOvqFqk Ls08RG30/n5p28AzmnRBl5Er5GTGe/7PHVeMQ4Iun4LLMppt5vs46zMdwj+c9YKfi4kC pXAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738865921; x=1739470721; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FJl7/XCq/mOYxrX7g6HKZEwMAdetJgh4DocsCwIosNE=; b=ljIKkg/t679Qo0Y5WntrvQrUAcGCEpf7PwodlGW40Sxx+Vt8Mdj6FL+afl5xp392Td VHAbUIDYZzGFM2KcxqcwHpQrecVlu1oIKQC2uvkLZ7tLjvXa4K15DKxjByh8TH5bb6ru Uf4tR6KR+H/6wEMcKmchlr8ZRQVOG/Od2R2XVU4E6jgbNP/FKWnEGOhz4qsT3M9nKtIA u+HU6MsiFjUbkMR1zJpy6XMZ97w8Npp3G2Jl1+/G6olyI62JXcPdOgI2D7TSTZ4W66ds PmoTgArts5jYkygOTxIynIxDO++0xkwjnkWo+sBtd6SjTjmpWrMAo07zX3iqNxSPocpH slNw== X-Gm-Message-State: AOJu0YyL63hD9tMC87xxabp/zT5nTgIXYnBtaF7JMIdD3AC/II6Jsaa0 hV+vnULLTpkaUMq9IQqSHG7Q4l8QFntJq4ZzBaDhrbxuVCIu0gSp6NdhrVa59tDdurLHXZBDICG oIHU= X-Gm-Gg: ASbGncuWHPFRhnR938OLoneeGYDaupVWP1C7+kp7PkPm8hcIMrliAxAeLOQWseBuEIB YKbAjRNJSFpsfWavaNXQ1VFp6WrRkXCWInqZJpw9V0rHe6bNvgOz28PnL+2zrCSo+eKD5o4L6xh jWNG3n8EIDezFTATv1Biu7K4i+ZOmP5eEBC0IORf+CzqUannlbqg8p+w+CDGF264p/TsgFpOtX+ z3eucREy6dLPypnvhY7F7cyQkKByKe8O16W48pOsJdqcThP0f14eN3bdLwv/q1Geb9TcWVtg37b T5H+5lMBYYrQ/ntDqpQVKv2K0nslfTn9ahI4OebuP7oEKDzUmfWBV0wxeEej5AtHLg== X-Received: by 2002:a05:600c:1e28:b0:437:c3a1:5fe7 with SMTP id 5b1f17b1804b1-439249abd7amr3524595e9.20.1738865919619; Thu, 06 Feb 2025 10:18:39 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390db11200sm61574155e9.38.2025.02.06.10.18.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h' Date: Thu, 6 Feb 2025 19:18:22 +0100 Message-ID: <20250206181827.41557-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "cpu.h" is target-specific. Definitions which can be used by hw/ code when building QOM blocks can be in "cpu-qom.h", which is target-agnostic. Move the MISA bits (removing the pointless target_ulong cast) and the IRQ index definitions. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu-qom.h | 40 ++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 24 ------------------------ target/riscv/cpu_bits.h | 15 --------------- 3 files changed, 40 insertions(+), 39 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index d56b067bf24..6028aa38fb2 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -55,4 +55,44 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) +/* Interrupt causes */ +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define RV(x) (1UL << (x - 'A')) + +/* + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] + * when adding new MISA bits here. + */ +#define RVI RV('I') +#define RVE RV('E') /* E and I are mutually exclusive */ +#define RVM RV('M') +#define RVA RV('A') +#define RVF RV('F') +#define RVD RV('D') +#define RVV RV('V') +#define RVC RV('C') +#define RVS RV('S') +#define RVU RV('U') +#define RVH RV('H') +#define RVG RV('G') +#define RVB RV('B') + +extern const uint32_t misa_bits[]; +const char *riscv_get_misa_ext_name(uint32_t bit); +const char *riscv_get_misa_ext_description(uint32_t bit); + #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97713681cbe..4e681ad3917 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -54,30 +54,6 @@ typedef struct CPUArchState CPURISCVState; */ #define RISCV_UW2_ALWAYS_STORE_AMO 1 -#define RV(x) ((target_ulong)1 << (x - 'A')) - -/* - * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] - * when adding new MISA bits here. - */ -#define RVI RV('I') -#define RVE RV('E') /* E and I are mutually exclusive */ -#define RVM RV('M') -#define RVA RV('A') -#define RVF RV('F') -#define RVD RV('D') -#define RVV RV('V') -#define RVC RV('C') -#define RVS RV('S') -#define RVU RV('U') -#define RVH RV('H') -#define RVG RV('G') -#define RVB RV('B') - -extern const uint32_t misa_bits[]; -const char *riscv_get_misa_ext_name(uint32_t bit); -const char *riscv_get_misa_ext_description(uint32_t bit); - #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) typedef struct riscv_cpu_profile { diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f97c48a3943..80701bc77fe 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -720,21 +720,6 @@ typedef enum RISCVException { #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff -/* Interrupt causes */ -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_VS_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_VS_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_VS_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_S_GEXT 12 -#define IRQ_PMU_OVF 13 #define IRQ_LOCAL_MAX 64 /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1)