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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d94d40csm62272665e9.9.2025.02.06.10.18.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 4/7] hw/riscv/boot: Use 'hwaddr' type for firmware addresses Date: Thu, 6 Feb 2025 19:18:24 +0100 Message-ID: <20250206181827.41557-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Some places already use the hwaddr type. Use it all over the API allows it to be target agnostic. Use cpu_env() in riscv_plic_hart_config_string() to shorten the access. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/riscv/boot.h | 21 ++++++++++----------- include/hw/riscv/boot_opensbi.h | 14 +++++++------- hw/riscv/boot.c | 28 ++++++++++++++-------------- 3 files changed, 31 insertions(+), 32 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 7d59b2e6c63..1f66432eaed 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -20,7 +20,6 @@ #ifndef RISCV_BOOT_H #define RISCV_BOOT_H -#include "exec/cpu-defs.h" #include "hw/loader.h" #include "hw/riscv/riscv_hart.h" @@ -43,21 +42,21 @@ bool riscv_is_32bit(RISCVHartArrayState *harts); char *riscv_plic_hart_config_string(int hart_count); void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts); -target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, - target_ulong firmware_end_addr); -target_ulong riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firmware, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb); +hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, + hwaddr firmware_end_addr); +hwaddr riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb); const char *riscv_default_firmware_name(RISCVHartArrayState *harts); char *riscv_find_firmware(const char *firmware_filename, const char *default_machine_firmware); -target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb); +hwaddr riscv_load_firmware(const char *firmware_filename, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb); void riscv_load_kernel(MachineState *machine, RISCVBootInfo *info, - target_ulong kernel_start_addr, + hwaddr kernel_start_addr, bool load_initrd, symbol_fn_t sym_cb); uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h index 18664a174b5..e6998c668ad 100644 --- a/include/hw/riscv/boot_opensbi.h +++ b/include/hw/riscv/boot_opensbi.h @@ -8,7 +8,7 @@ #ifndef RISCV_BOOT_OPENSBI_H #define RISCV_BOOT_OPENSBI_H -#include "exec/cpu-defs.h" +#include "exec/hwaddr.h" /** Expected value of info magic ('OSBI' ascii string in hex) */ #define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f @@ -31,15 +31,15 @@ enum sbi_scratch_options { /** Representation dynamic info passed by previous booting stage */ struct fw_dynamic_info { /** Info magic */ - target_long magic; + hwaddr magic; /** Info version */ - target_long version; + hwaddr version; /** Next booting stage address */ - target_long next_addr; + hwaddr next_addr; /** Next booting stage mode */ - target_long next_mode; + hwaddr next_mode; /** Options for OpenSBI library */ - target_long options; + hwaddr options; /** * Preferred boot HART id * @@ -55,7 +55,7 @@ struct fw_dynamic_info { * stage can set it to -1UL which will force the FW_DYNAMIC firmware * to use the relocation lottery mechanism. */ - target_long boot_hart; + hwaddr boot_hart; }; /** Representation dynamic info passed by previous booting stage */ diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c309441b7d8..acc0d221fce 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -21,7 +21,6 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/error-report.h" -#include "exec/cpu-defs.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/riscv/boot.h" @@ -31,6 +30,7 @@ #include "system/qtest.h" #include "system/kvm.h" #include "system/reset.h" +#include "target/riscv/cpu.h" #include @@ -51,7 +51,7 @@ char *riscv_plic_hart_config_string(int hart_count) for (i = 0; i < hart_count; i++) { CPUState *cs = qemu_get_cpu(i); - CPURISCVState *env = &RISCV_CPU(cs)->env; + CPURISCVState *env = cpu_env(cs); if (kvm_enabled()) { vals[i] = "S"; @@ -74,8 +74,8 @@ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) info->is_32bit = riscv_is_32bit(harts); } -target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, - target_ulong firmware_end_addr) { +hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, + hwaddr firmware_end_addr) { if (info->is_32bit) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); } else { @@ -133,13 +133,13 @@ char *riscv_find_firmware(const char *firmware_filename, return filename; } -target_ulong riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firmware, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb) +hwaddr riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb) { char *firmware_filename; - target_ulong firmware_end_addr = *firmware_load_addr; + hwaddr firmware_end_addr = *firmware_load_addr; firmware_filename = riscv_find_firmware(machine->firmware, default_machine_firmware); @@ -154,11 +154,11 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, return firmware_end_addr; } -target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb) +hwaddr riscv_load_firmware(const char *firmware_filename, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb) { - uint64_t firmware_entry, firmware_end; + hwaddr firmware_entry, firmware_end; ssize_t firmware_size; g_assert(firmware_filename != NULL); @@ -227,7 +227,7 @@ static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info) void riscv_load_kernel(MachineState *machine, RISCVBootInfo *info, - target_ulong kernel_start_addr, + hwaddr kernel_start_addr, bool load_initrd, symbol_fn_t sym_cb) {