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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43907f16ffasm58795995e9.1.2025.02.06.10.18.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 5/7] hw/riscv/iommu: Reduce needs for target-specific code Date: Thu, 6 Feb 2025 19:18:25 +0100 Message-ID: <20250206181827.41557-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the qemu_target_page_size() runtime function instead of the TARGET_PAGE_SIZE definition, remove unnecessary "exec/exec-all.h" header. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/riscv-iommu-pci.c | 5 +++-- hw/riscv/riscv-iommu-sys.c | 1 - hw/riscv/riscv-iommu.c | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c index 12451869e41..d8779481421 100644 --- a/hw/riscv/riscv-iommu-pci.c +++ b/hw/riscv/riscv-iommu-pci.c @@ -22,13 +22,13 @@ #include "hw/pci/pci_bus.h" #include "hw/qdev-properties.h" #include "hw/riscv/riscv_hart.h" +#include "exec/target_page.h" #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/host-utils.h" #include "qom/object.h" -#include "cpu_bits.h" #include "riscv-iommu.h" #include "riscv-iommu-bits.h" #include "trace.h" @@ -102,7 +102,8 @@ static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp) qdev_realize(DEVICE(iommu), NULL, errp); memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0", - QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE)); + QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), + qemu_target_page_size())); memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr); pcie_endpoint_cap_init(dev, 0); diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c index 65b24fb07de..bbe839ed241 100644 --- a/hw/riscv/riscv-iommu-sys.c +++ b/hw/riscv/riscv-iommu-sys.c @@ -26,7 +26,6 @@ #include "qemu/host-utils.h" #include "qemu/module.h" #include "qom/object.h" -#include "exec/exec-all.h" #include "trace.h" #include "riscv-iommu.h" diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index e7568ca227a..fb763e6e69d 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qemu/timer.h" +#include "target/riscv/cpu.h" #include "cpu_bits.h" #include "riscv-iommu.h" #include "riscv-iommu-bits.h"