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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc9ef8ac6sm4922432f8f.27.2025.02.08.08.39.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Feb 2025 08:39:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , qemu-arm@nongnu.org, Mark Cave-Ayland , =?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= , Peter Maydell , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v6 5/7] hw/char/pl011: Consider TX FIFO overrun error Date: Sat, 8 Feb 2025 17:39:09 +0100 Message-ID: <20250208163911.54522-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250208163911.54522-1-philmd@linaro.org> References: <20250208163911.54522-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When transmission is disabled, characters are still queued to the FIFO which eventually overruns. Report that error condition in the status register. Signed-off-by: Philippe Mathieu-Daudé --- hw/char/pl011.c | 20 ++++++++++++++++++++ hw/char/trace-events | 2 ++ 2 files changed, 22 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 447f185e2d5..ef39ab666a2 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -61,6 +61,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) /* Data Register, UARTDR */ #define DR_BE (1 << 10) +/* Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ +#define RSR_OE (1 << 3) + /* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ #define INT_OE (1 << 10) #define INT_BE (1 << 9) @@ -158,6 +161,16 @@ static inline unsigned pl011_get_fifo_depth(PL011State *s) return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; } +static bool pl011_is_tx_fifo_full(PL011State *s) +{ + if (pl011_is_fifo_enabled(s)) { + trace_pl011_fifo_tx_is_full("FIFO", fifo8_is_full(&s->xmit_fifo)); + return fifo8_is_full(&s->xmit_fifo); + } + trace_pl011_fifo_tx_is_full("CHAR", !fifo8_is_empty(&s->xmit_fifo)); + return !fifo8_is_empty(&s->xmit_fifo); +} + static inline void pl011_reset_rx_fifo(PL011State *s) { s->read_count = 0; @@ -264,6 +277,13 @@ static void pl011_write_txdata(PL011State *s, uint8_t data) "PL011 data written to disabled TX UART\n"); } + if (pl011_is_tx_fifo_full(s)) { + /* The FIFO is already full. Content remains valid. */ + trace_pl011_fifo_tx_overrun(); + s->rsr |= RSR_OE; + return; + } + trace_pl011_fifo_tx_put(data); pl011_loopback_tx(s, data); fifo8_push(&s->xmit_fifo, data); diff --git a/hw/char/trace-events b/hw/char/trace-events index dd635ac6012..8234f3afa13 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -67,9 +67,11 @@ pl011_fifo_enable(bool enable) "enable:%u" pl011_fifo_is_enabled(bool enabled) "enabled:%u" pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now %d" pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set" +pl011_fifo_tx_is_full(const char *desc, bool full) "mode:%s full:%u" pl011_fifo_tx_put(uint8_t byte) "TX FIFO push char [0x%02x]" pl011_fifo_tx_xmit_used(unsigned sent) "TX FIFO used %u chars" pl011_fifo_tx_xmit_consumed(unsigned sent) "TX FIFO consumed %u chars" +pl011_fifo_tx_overrun(void) "TX FIFO overrun" pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")" # cmsdk-apb-uart.c