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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e4844c0dsm18818713f8f.80.2025.03.04.16.53.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Mar 2025 16:53:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Pierrick Bouvier , =?utf-8?q?Daniel_P=2E_Berra?= =?utf-8?q?ng=C3=A9?= , Richard Henderson , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [RFC PATCH 10/11] qemu: Introduce qemu_arch_name() helper Date: Wed, 5 Mar 2025 01:52:24 +0100 Message-ID: <20250305005225.95051-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250305005225.95051-1-philmd@linaro.org> References: <20250305005225.95051-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce a generic helper to get the target name of a QemuArchBit. (This will be used for single / heterogeneous binaries). Use it in target_name(), removing the last use of the TARGET_NAME definition. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/arch_info.h | 2 ++ arch_info-target.c | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/include/qemu/arch_info.h b/include/qemu/arch_info.h index 613dc2037db..7e3192f590f 100644 --- a/include/qemu/arch_info.h +++ b/include/qemu/arch_info.h @@ -46,6 +46,8 @@ typedef enum QemuArchBit { #define QEMU_ARCH_LOONGARCH BIT(QEMU_ARCH_BIT_LOONGARCH) #define QEMU_ARCH_ALL -1 +const char *qemu_arch_name(QemuArchBit qemu_arch_bit); + const char *target_name(void); bool qemu_arch_available(unsigned qemu_arch_mask); diff --git a/arch_info-target.c b/arch_info-target.c index 61007415b30..9b19fe8d56d 100644 --- a/arch_info-target.c +++ b/arch_info-target.c @@ -24,9 +24,41 @@ #include "qemu/osdep.h" #include "qemu/arch_info.h" +const char *qemu_arch_name(QemuArchBit qemu_arch_bit) +{ + static const char *legacy_target_names[] = { + [QEMU_ARCH_ALPHA] = "alpha", + [QEMU_ARCH_BIT_ARM] = TARGET_LONG_BITS == 32 ? "arm" : "aarch64", + [QEMU_ARCH_BIT_AVR] = "avr", + [QEMU_ARCH_BIT_HEXAGON] = "hexagon", + [QEMU_ARCH_BIT_HPPA] = "hppa", + [QEMU_ARCH_BIT_I386] = TARGET_LONG_BITS == 32 ? "i386" : "x86_64", + [QEMU_ARCH_BIT_LOONGARCH] = "loongarch64", + [QEMU_ARCH_BIT_M68K] = "m68k", + [QEMU_ARCH_BIT_MICROBLAZE] = TARGET_BIG_ENDIAN ? "microblaze" + : "microblazeel", + [QEMU_ARCH_BIT_MIPS] = TARGET_BIG_ENDIAN + ? (TARGET_LONG_BITS == 32 ? "mips" : "mips64") + : (TARGET_LONG_BITS == 32 ? "mipsel" : "mips64el"), + [QEMU_ARCH_BIT_OPENRISC] = "or1k", + [QEMU_ARCH_BIT_PPC] = TARGET_LONG_BITS == 32 ? "ppc" : "ppc64", + [QEMU_ARCH_BIT_RISCV] = TARGET_LONG_BITS == 32 ? "riscv32" : "riscv64", + [QEMU_ARCH_BIT_RX] = "rx", + [QEMU_ARCH_BIT_S390X] = "s390x", + [QEMU_ARCH_BIT_SH4] = TARGET_BIG_ENDIAN ? "sh4eb" : "sh4", + [QEMU_ARCH_BIT_SPARC] = TARGET_LONG_BITS == 32 ? "sparc" : "sparc64", + [QEMU_ARCH_BIT_TRICORE] = "tricore", + [QEMU_ARCH_BIT_XTENSA] = TARGET_BIG_ENDIAN ? "xtensaeb" : "xtensa", + }; + + assert(qemu_arch_bit < ARRAY_SIZE(legacy_target_names)); + assert(legacy_target_names[qemu_arch_bit]); + return legacy_target_names[qemu_arch_bit]; +} + const char *target_name(void) { - return TARGET_NAME; + return qemu_arch_name(QEMU_ARCH_BIT); } bool qemu_arch_available(unsigned qemu_arch_mask)