From patchwork Thu Mar 6 16:39:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 870893 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp352339wri; Thu, 6 Mar 2025 08:44:05 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXKnMkJKwXgtKrV0DxFV6H7XKtP3D35k13k9t4C98AivPzl1IyRc95D/tmoPG50p/BOeYVBcg==@linaro.org X-Google-Smtp-Source: AGHT+IHvxvDjEhfdwiMBgJFjY8dWjN1I3DypiZ4GV7Eg7fosYTvgXSfFonSjfMRgWDaEdPjXZXOZ X-Received: by 2002:a05:620a:2b96:b0:7c3:ccf5:363e with SMTP id af79cd13be357-7c3d8dd04dcmr1254295285a.13.1741279445705; Thu, 06 Mar 2025 08:44:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741279445; cv=none; d=google.com; s=arc-20240605; b=a0eSqFXnwX6kqVRrZTToJsp2eveG3GJbWkxPqlPYUP/S+WAN44qk/eCdh07+/tV0lo IE4iLs8RGZ/7sEvb1ervGBRS7aQn/k6fslfSIUD1Tm2RKdaxsbofd39Tu56cfIRiTOnm l98ysUTBxVYfIp83kpC143NBrQrQutg1jvbSOH0O603pqKQEcCKpQUBUK2T2PHVpmTHg Ex9j5t8tMadpr+SOAV5PB2rv57YQ6H2w8zXHB9WIH0l6WeYfMwJlo806hHoNkLzlvCCw YY3AzkKW2Q3JW+4906OSRAyJA4n59gdvdgwzlJjN8fjegx08eNUBXkrIBZ+YXKIycSuJ JNwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0WIG0SaEOnTT7Vl+CcOLcRx6EDCmK/EJvLZA/gTBtzQ=; fh=VXWJj3eY3IYmsqiWU9bYySUNObPhZHMgXbbY6+YodPw=; b=O71tMaMdv249kydSvRYFCvmCEFh+ANcUjPtMkTK9rEVbmqa62ulOM3rPh0VcRUZC4x CzAF3hzhHkfRNkmlQEA5Lz3rtv3mwYSLbdT13Ci9L2tGol3vcf1tlk4WnAV2QfLWYEp+ YlDP/G8ifecHNeFkRgiVkzLZxwLXzNv2CKOCHtESmTd6IIWPiWAk0GNB5QwHbM8RR57Q NNKsZQ0ChSekZ++iQGwMTRMXvU/Z9TCAyQ+9Jf3Gz/kPpkzdErIwfobRWFdSqirsZBrH pMFfMwjBxzMndPhN+pKfVmeh2QB4nGaXQnN1LTfKh37zipfCvcC0malMHOWAy9jM7RoS aj3A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HOUs+GU0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c3e54fee57si151546585a.213.2025.03.06.08.44.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Mar 2025 08:44:05 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HOUs+GU0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqEG8-0006sm-Ik; Thu, 06 Mar 2025 11:39:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqEG2-0006no-AD for qemu-devel@nongnu.org; Thu, 06 Mar 2025 11:39:39 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqEG0-0004bh-A1 for qemu-devel@nongnu.org; Thu, 06 Mar 2025 11:39:37 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-43bc38bb6baso5709905e9.3 for ; Thu, 06 Mar 2025 08:39:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741279174; x=1741883974; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0WIG0SaEOnTT7Vl+CcOLcRx6EDCmK/EJvLZA/gTBtzQ=; b=HOUs+GU02ulIkn54U9ZPk0a4nSMACpeUf9svog4JIY4UKovzPG5xkL/jI6JHiLPhaD mm3ZCM91PFWj7y2llp2HpM+kL1Ja43vYqhX1WZeQ9D2hg2YZy6hSSxYg4kjevtmuK2Wc NZ1A9WXfOmgGdSBCvVSixCHscWwp+NyP2JyJjjTgfhWM5M9TCU7nac+8wMcRBYtmGUt8 kaKgIgEn/5UaQeKYbpAGw8dMsdhoR15aNpmSb92upTIMpDSvbeHe8VfMp5Pu0YE8uGGb PDQwdxFoHEcC6oUaKHqASPcLhY1ztbgXD7V+0NkdxVD9eCLEbFQ+7cxsKM6icA+MVLfJ ED2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741279174; x=1741883974; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0WIG0SaEOnTT7Vl+CcOLcRx6EDCmK/EJvLZA/gTBtzQ=; b=NBC7IGq30gW7mfs2EPVU/91IKzP2bbPiiAp0QZNw5X0bq004ZE2CllNgUBWrhCVYqt TYR5qYwBCfgruUulRlrg0iG5CfbE5Fu5dmCUFi7QJC7JaBW43QnMXw96dbEOSMld2ign oa8f5xJKOYBhAw8ev7M60wuFh0dW7MfB+gkx6is5Es/i6zS1XLLY3MI/jq3spLz40xmh ytka3bsUb/2l9BE6AHuHEhQlt2xs6h1NMvYrPNjghcyJ80yum+OqtI4sC5+6FxEPODNU LtYf1Uk++fH+VV/AN0+ezCy7tYJk+0hSEElavgHfciGyTPuvHiET0HLss3fmqQ+WrC/d K+hA== X-Forwarded-Encrypted: i=1; AJvYcCWCt1bmumc2Q9dVKYXWNEwjI6WDfsBd898edjsJpiFat87/fbqOpw2HfFJujyBcas1/O+PHtGsH3d9n@nongnu.org X-Gm-Message-State: AOJu0Yw+LLsvsJ/T8vfhyNGSroy7xhkDJkhvK0Cd9P8Xz2FovwN3zEnQ 8GeKY4Q6M7Z9Txksu05CLXzQQgRzxCgW+qyuSHPnQIGOirhFtROU8I4epfkzYgoMWiixS+5g/2S I X-Gm-Gg: ASbGnct5osxGs5xALacJVW+a4c0uxGI6nV/V+QpoBovhZPAzHdO98rxnjFhvz73Ujc5 aeCbkRbdT2amCQiIvQQ71onIHIF+MuSO8cGJqKfKPKD9qc5Dkmw1mH7ODdBHOWnBNHsmb0Qemwq rZHiDMdywChMTX5MviP72/AporDTi8/eGmhXm+7qC42wBuCqMYpmxrs5CsxcKr8/NuHeMokVCfQ ldgmyFAjP0zaZArlwgVA3hIf/txVNZbu7YtFuKsGOfH40gG2DpXC1ENfw7mWRxeqDtbcpOzE1rZ bHoUBxgwyxbsLYXaHbqx0aKQI43gTFx+LLe9AIVT6ALP0o3i6Rk= X-Received: by 2002:a5d:64cf:0:b0:390:fe13:e0ba with SMTP id ffacd0b85a97d-3911f756fd2mr7745130f8f.27.1741279174616; Thu, 06 Mar 2025 08:39:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/10] target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32 Date: Thu, 6 Mar 2025 16:39:22 +0000 Message-ID: <20250306163925.2940297-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to be RAO/WI. We don't enforce this. This isn't a problem yet because at the moment all of our CPU types with AArch64 support AArch32 at all exception levels, but in the future this is likely to no longer be true. Enforce the RAO/WI behaviour. Note that we handle "reset value should honour RES1 bits" in the same way that SCR_EL3 does, via a reset function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1085bff0ec5..6dc6f3858fc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5167,6 +5167,11 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) /* Clear RES0 bits. */ value &= valid_mask; + /* RW is RAO/WI if EL1 is AArch64 only */ + if (!cpu_isar_feature(aa64_aa32_el1, cpu)) { + value |= HCR_RW; + } + /* * These bits change the MMU setup: * HCR_VM enables stage 2 translation @@ -5224,6 +5229,12 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); } +static void hcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* hcr_write will set the RES1 bits on an AArch64-only CPU */ + hcr_write(env, ri, 0); +} + /* * Return the effective value of HCR_EL2, at the given security state. * Bits that are not included here: @@ -5459,6 +5470,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), .nv2_redirect_offset = 0x78, + .resetfn = hcr_reset, .writefn = hcr_write, .raw_writefn = raw_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, .type = ARM_CP_ALIAS | ARM_CP_IO,