diff mbox series

[Stable-9.2.3,32/51] target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer

Message ID 20250315061801.622606-32-mjt@tls.msk.ru
State New
Headers show
Series [Stable-9.2.3,01/51] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1 | expand

Commit Message

Michael Tokarev March 15, 2025, 6:17 a.m. UTC 
From: Peter Maydell <peter.maydell@linaro.org>

The CNTVOFF_EL2 offset register should only be applied for accessses
to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*).  We were
incorrectly applying it for the EL2 virtual timer (CNTHV_*).

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250204125009.2281315-3-peter.maydell@linaro.org
(cherry picked from commit 5709038aa8b4d58b8c201ed53c327074173a35c6)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 417801d9c3..404ef983f3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2871,7 +2871,6 @@  static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
 
     switch (timeridx) {
     case GTIMER_VIRT:
-    case GTIMER_HYPVIRT:
         offset = gt_virt_cnt_offset(env);
         break;
     case GTIMER_PHYS:
@@ -2891,7 +2890,6 @@  static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     switch (timeridx) {
     case GTIMER_VIRT:
-    case GTIMER_HYPVIRT:
         offset = gt_virt_cnt_offset(env);
         break;
     case GTIMER_PHYS: