From patchwork Sat Mar 15 07:42:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 873855 Delivered-To: patch@linaro.org Received: by 2002:a5d:4308:0:b0:38f:210b:807b with SMTP id h8csp1080955wrq; Sat, 15 Mar 2025 00:46:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWitYMnrP4SfgLZVRd0mNVZs1bi1EzWVXMGzW2gshjc4RprJbaVvRA4Boo40iPg5htKLz/VFQ==@linaro.org X-Google-Smtp-Source: AGHT+IGGkiunxTGk8mXSuTb2rGj4tUzX+q3n2ScAa5VV+Z/xA1RLbB6vsZCuhkgX5KmP0dlJilIx X-Received: by 2002:ac8:590b:0:b0:476:80ce:a614 with SMTP id d75a77b69052e-476c814a1camr83766201cf.19.1742024797324; Sat, 15 Mar 2025 00:46:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1742024797; cv=none; d=google.com; s=arc-20240605; b=aqjnlrVdRiY4VAuL1KlXJ/cKy3Q/v3/Qz8XN/40z7znShXpcvaUFmndStwgc0eeUF1 HRWpsv1tK+C1kV2lK/dtpFl7joiigz1c6LBH6eMYo87XQrM/ayADmaslusM33ycDZyR8 qiKNhU3ESACTh32ADN31pv1Km8vNTJKZc93EsJABEtTa/rA0Dit80QamHoesxj6s0sVi W24T9LBpRESEom8mjtMxlLZkzXBaidBpxOcL2w7eTu0h6pafaOmWmRtJB9fKk0rZNe+7 CTfZb9jXOTF1e0IrGxbQTVxSDn1rIBCWVSNZt0oOK8t14r+DXtuPUCSae7AcjGF/QRHB MJ8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=xdAGl00dVyw1SjWAruqa6Pj0qUccNQ4RQdnWOvDKNSI=; fh=upfN+4mcRAuX+bX9oPqMwq1TP+fTfKlWZBqspF+lG6I=; b=D77wWZX3RasBXiWmAXbNhfrRnDvxS53fQ9Nfg4/PpyMUp1x28AH6/OBmSOZUv/7aDL qY4Z4bGzopJ8orUoZh3uaPXhjTJv1RTgmaUUEr1AszgDrKJ2TxwN1jT0M0Y6fnqvoQAt 4yc97AJgUK+npO7LiJxUvluxWG5Xbv5YdTfUWfMuecImkfujL7Qp6nQ1ooH8lvmSs9lt tEBp+gOdHiHELYdsTC1RGVfaBMGyrwLRJXllK72LHrQsv24FRAdy0UOLs9YFQLh3YgOC XOZipo/7m+hyX6FZqVbubXrlxr15a8Kv85F+/yVMo0b06reEPYNm7o1wW9jBfm+7+Jqa omWQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-476bb6147ecsi51313851cf.21.2025.03.15.00.46.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Mar 2025 00:46:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ttMBK-0002iw-EJ; Sat, 15 Mar 2025 03:43:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ttMBI-0002fi-8P; Sat, 15 Mar 2025 03:43:40 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ttMBG-0004wX-IM; Sat, 15 Mar 2025 03:43:39 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id B6185FFB02; Sat, 15 Mar 2025 10:41:55 +0300 (MSK) Received: from gandalf.tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with ESMTP id A4CAE1CACCC; Sat, 15 Mar 2025 10:42:49 +0300 (MSK) Received: by gandalf.tls.msk.ru (Postfix, from userid 1000) id 79B32559F0; Sat, 15 Mar 2025 10:42:49 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Michael Tokarev Subject: [Stable-8.2.10 14/42] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3 Date: Sat, 15 Mar 2025 10:42:16 +0300 Message-Id: <20250315074249.634718-14-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell In the gicv3_{irq,fiq,irqfiq}_access() functions, there is a check which downgrades a CP_ACCESS_TRAP_EL3 to CP_ACCESS_TRAP if EL3 is not AArch64. This has been there since the GIC was first implemented, but it isn't right: if we are trapping because of SCR.IRQ or SCR.FIQ then we definitely want to be going to EL3 (doing AArch32.TakeMonitorTrapException() in pseudocode terms). We might want to not take a trap at all, but we don't ever want to go to the default target EL, because that would mean, for instance, taking a trap to Hyp mode if the trapped access was made from Hyp mode. (This might have been an attempt to work around our failure to properly implement Monitor Traps.) Remove the bogus check. Cc: qemu-stable@nongnu.org Fixes: 359fbe65e01e ("hw/intc/arm_gicv3: Implement GICv3 CPU interface registers") Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20250130182309.717346-7-peter.maydell@linaro.org (cherry picked from commit d04c6c3c000ab3e588a2b91641310aeea89408f7) Signed-off-by: Michael Tokarev diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 8eacf4101c..f2440597ea 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2099,9 +2099,6 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env, } } - if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { - r = CP_ACCESS_TRAP; - } return r; } @@ -2164,9 +2161,6 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env, } } - if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { - r = CP_ACCESS_TRAP; - } return r; } @@ -2203,9 +2197,6 @@ static CPAccessResult gicv3_irq_access(CPUARMState *env, } } - if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { - r = CP_ACCESS_TRAP; - } return r; }