From patchwork Tue Apr 15 19:24:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 881275 Delivered-To: patch@linaro.org Received: by 2002:adf:f902:0:b0:38f:210b:807b with SMTP id b2csp631522wrr; Tue, 15 Apr 2025 12:51:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWfQCh1S9ZhnjHRj1QgAEgLPUr26Um+tf2Bfi5Das/os1ODfQSoFJvtgVGV2rsUwI9WUElqTg==@linaro.org X-Google-Smtp-Source: AGHT+IGXM7BAkCyvXg4dZJsBn3uUXOSjXP9eSb8L+iMJ4IeUK2ccU6F+FZvBNJL0AqEWkPg2P9es X-Received: by 2002:a05:622a:134f:b0:476:6189:4f2b with SMTP id d75a77b69052e-47ad3ae2f42mr10552381cf.46.1744746662949; Tue, 15 Apr 2025 12:51:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744746662; cv=none; d=google.com; s=arc-20240605; b=Wyhx2aDyDIOySIGorGQjsRZQvEHc8b7ioscBpjz+Y5eCwnali6+OBxMaj8aUvFCX8B p9TnYPS2lF7ayqIoyLthHR3pgC8oDfZZHHAzIo45pAVBlxsbUwNkrULsficVcY8ufllt /RZiC+yJSQuvYg3EbURqT69HKmMBkuYvA76eIM0Lq7zUl+CKTfyufoX8nPRuMnufKbHX o98s1ffYh8Awl5Z0sJU9LdBV8ZzDGxf57YUDQ94T67WzdcZRuc13Z9oaJtU5oIng0jym fkqh5+BMLmBxVk4VYhExFhLsIGGVD4dwfVCnT9HTYPkYeinWOjs6jCqaT2mDtteAai4a XMYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xYaHSVpuuJwemQCux86oN8VsMmNwcQA05yBYxPQ4D2Q=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=jcsu0UbyCF7lFDg/NfoIJb1RhuyY7xMDetp3SkVsc/785ZexfYJobb3akRI+ePfaD2 pa67oIntwH05Kb84liQzYaAYI4J7MkZOgd8UW1B+A87x8ue0onvvlgD7rvNozOZC/6/4 GxO32zaZhpiBN69kLsgtD35KI+hhJcydauG5siT/unuLEh5QJNDXnhxiaHn7TXpcMiZi cKwh4uP3oDnClNd1p/X35QV9KZFM+yPfRvwzmnIKYSrr1I8YgNkE09viGpgszhODq88L Y8OEAvZMVUzUN++yNQzCCPQpC97FIlyuN1DDaaXsBD3T/dPOnseHUEuqmJglrGOpKSpJ fLGw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LqiZ7ObN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4796eb0da56si120966071cf.25.2025.04.15.12.51.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 Apr 2025 12:51:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LqiZ7ObN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u4mIL-0004vr-I9; Tue, 15 Apr 2025 15:50:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u4mC5-0001ph-CV for qemu-devel@nongnu.org; Tue, 15 Apr 2025 15:43:42 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u4mBz-0008PY-46 for qemu-devel@nongnu.org; Tue, 15 Apr 2025 15:43:40 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-7376e311086so7847766b3a.3 for ; Tue, 15 Apr 2025 12:43:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744746209; x=1745351009; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xYaHSVpuuJwemQCux86oN8VsMmNwcQA05yBYxPQ4D2Q=; b=LqiZ7ObNM2qfnBoH1xevwcle52yfnwd8l/hce6YPNLlA0cpqwrIXSNVUkqG8umiRvF 5B+6SFQ8cBpp4w3TJd+QhtTcHAqMCteJLh2z1EH6rzUvBUb7NZV4XsgxP1qAXNYtWDi3 8qeu8XAv6d/Y7udXFWWX42josuVfxuKr+dinAkx6msYXVRKDlDZPbsb3+NaSj8eDT/OZ 3hKQhwV88o+QLi5YTisrWnxFMerjkSf2+UQqYozMKoTKA7Tmj4ZhCFVI6lPX2meNqR6s uLfOfTk3UptXTeIKOxqghrNytkpQYAG12sVU2uGBPCQ8nupYhGkCcqshH5KVF1o5991g ypGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744746209; x=1745351009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xYaHSVpuuJwemQCux86oN8VsMmNwcQA05yBYxPQ4D2Q=; b=seMqXfmlpvQEp9ozYnvrBpf23w0ELuNTSNmqZMV34NETsfYlLRVzNW8FqK/o9W+KKm 9xCx9rYJ4zNrCIHrmVPUEwif/tZnOGqx3fqoRs5OknHKcOjy9LKnxSNnElkCr1HX1lxg tV/MTSnKXe9E2KgwoGzGCtgZCpkNqc0iX20JG3VudGavNZNqiMLd5RvXLPsZC0B2yKBM 2kuuIxY3FkbdpgfMPV5FxwQy+enwup7+FHVyLKU4K0iVFk6kQtVNlLjCmKdyclNl9HG4 BdKrcbFR/f57hD+vSWOlX0VD/kx/KJrJk6ZBPQTHLyDU6NnSWzzV/y+QGF0AUnGNam37 xNiA== X-Gm-Message-State: AOJu0Yy2frpE+IR/yElYvFoZ2Az9VLRCJ4vvO/buvlVS5O8DOq1PivoG 2BU8ZMdZZRdHFS2jMarD9q70Cq4pSKbDXZVwCEAC7qiRn38nQ5pZvj7qLxlTLIHbZGnctVD1EmL 2 X-Gm-Gg: ASbGncsQmPjj2ne4ipGJgcM5luxXeGtOU70mURaKrQra8Vj2PXOANQgCDC+bChzVJE/ rxCDHpJbDmv4sc2or47n+ifty0g4QhvK+kkK7ecIySNy2xhenRyl48/IakiH45qcXMbrbYIOO+Y ioDNVnmbdfHdc3IFWMh9VRQQjRQjbgKMbBfTnjCazx5Y8zzXNKXUtKZJd0V/UeQN65dHM4c0T4E T8yXtlwZgLrc7vEq/7TpsXLlcBMOQpOpW7Q3apcsKC97TXSBjS8BOnlGqyo7Rl2LksS/Fb/cL5E GmE5AH/2HFs1nThdakY6btxoSAxtCK4hvzKNMB8MQ/E5ZT5Bfs3p9slOMdkgTvjjTfmhixTiUjw = X-Received: by 2002:a17:902:ba95:b0:224:194c:6942 with SMTP id d9443c01a7336-22c31a86b63mr4159995ad.34.1744745775397; Tue, 15 Apr 2025 12:36:15 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73bd230e34asm9155603b3a.137.2025.04.15.12.36.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Apr 2025 12:36:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 143/163] tcg/s390x: Remove support for add2/sub2 Date: Tue, 15 Apr 2025 12:24:54 -0700 Message-ID: <20250415192515.232910-144-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250415192515.232910-1-richard.henderson@linaro.org> References: <20250415192515.232910-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We have replaced this with support for add/sub carry. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- tcg/s390x/tcg-target-con-set.h | 2 -- tcg/s390x/tcg-target-has.h | 8 +++--- tcg/s390x/tcg-target.c.inc | 50 ---------------------------------- 3 files changed, 4 insertions(+), 56 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 0a991f6d5d..f67fd7898e 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -45,5 +45,3 @@ C_O2_I1(o, m, r) C_O2_I2(o, m, 0, r) C_O2_I2(o, m, r, r) C_O2_I3(o, m, 0, 1, r) -C_N1_O1_I4(r, r, 0, 1, ri, r) -C_N1_O1_I4(r, r, 0, 1, rUV, r) diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h index 4a2b71995d..17e61130cd 100644 --- a/tcg/s390x/tcg-target-has.h +++ b/tcg/s390x/tcg-target-has.h @@ -29,13 +29,13 @@ extern uint64_t s390_facilities[3]; ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1) /* optional instructions */ -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 +#define TCG_TARGET_HAS_add2_i32 0 +#define TCG_TARGET_HAS_sub2_i32 0 #define TCG_TARGET_HAS_extr_i64_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 +#define TCG_TARGET_HAS_add2_i64 0 +#define TCG_TARGET_HAS_sub2_i64 0 #define TCG_TARGET_HAS_qemu_ldst_i128 1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 36293d0f42..09c7ca5b44 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3064,23 +3064,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); break; - case INDEX_op_add2_i32: - if (const_args[4]) { - tcg_out_insn(s, RIL, ALFI, args[0], args[4]); - } else { - tcg_out_insn(s, RR, ALR, args[0], args[4]); - } - tcg_out_insn(s, RRE, ALCR, args[1], args[5]); - break; - case INDEX_op_sub2_i32: - if (const_args[4]) { - tcg_out_insn(s, RIL, SLFI, args[0], args[4]); - } else { - tcg_out_insn(s, RR, SLR, args[0], args[4]); - } - tcg_out_insn(s, RRE, SLBR, args[1], args[5]); - break; - case INDEX_op_br: tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); break; @@ -3124,31 +3107,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); break; - case INDEX_op_add2_i64: - if (const_args[4]) { - if ((int64_t)args[4] >= 0) { - tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); - } else { - tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); - } - } else { - tcg_out_insn(s, RRE, ALGR, args[0], args[4]); - } - tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); - break; - case INDEX_op_sub2_i64: - if (const_args[4]) { - if ((int64_t)args[4] >= 0) { - tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); - } else { - tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); - } - } else { - tcg_out_insn(s, RRE, SLGR, args[0], args[4]); - } - tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); - break; - case INDEX_op_mb: /* The host memory model is quite strong, we simply need to serialize the instruction stream. */ @@ -3643,14 +3601,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_qemu_st_i128: return C_O0_I3(o, m, r); - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: - return C_N1_O1_I4(r, r, 0, 1, ri, r); - - case INDEX_op_add2_i64: - case INDEX_op_sub2_i64: - return C_N1_O1_I4(r, r, 0, 1, rUV, r); - case INDEX_op_st_vec: return C_O0_I2(v, r); case INDEX_op_ld_vec: