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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4a4c8fsm1109311f8f.89.2025.04.17.17.51.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 17 Apr 2025 17:51:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , qemu-devel@nongnu.org Cc: Anton Johansson , Richard Henderson Subject: [RFC PATCH v2 10/11] hw/arm/aspeed: Build objects once Date: Fri, 18 Apr 2025 02:50:58 +0200 Message-ID: <20250418005059.4436-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418005059.4436-1-philmd@linaro.org> References: <20250418005059.4436-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_XBL=0.375, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than Aspeed machines can be filtered when running a qemu-system-arm or qemu-system-aarch64 binary, we can remove the TARGET_AARCH64 #ifdef'ry and compile the aspeed.c file once, moving it from arm_ss[] source set to arm_common_ss[]. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed.c | 6 ------ hw/arm/meson.build | 4 ++-- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index d54ee2d4b53..363be2daf60 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -179,13 +179,11 @@ struct AspeedMachineState { #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 -#ifdef TARGET_AARCH64 /* AST2700 evb hardware value */ /* SCU HW Strap1 */ #define AST2700_EVB_HW_STRAP1 0x00000800 /* SCUIO HW Strap1 */ #define AST2700_EVB_HW_STRAP2 0x00000700 -#endif /* Rainier hardware value: (QEMU prototype) */ #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) @@ -1663,7 +1661,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } -#ifdef TARGET_AARCH64 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -1713,7 +1710,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); } -#endif static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, void *data) @@ -1936,7 +1932,6 @@ static const TypeInfo aspeed_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700a0-evb"), .parent = TYPE_ASPEED_MACHINE, @@ -1953,7 +1948,6 @@ static const TypeInfo aspeed_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#endif }, { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 09b1cfe5b57..f76e7fb229f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -39,15 +39,15 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) -arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( +arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed.c', 'aspeed_soc_common.c', 'aspeed_ast2400.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', + 'aspeed_ast27x0.c', 'aspeed_eeprom.c', 'fby35.c')) -arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))