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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 095/147] hw/core/cpu: Remove CPUClass::mmu_index() Date: Tue, 22 Apr 2025 12:27:24 -0700 Message-ID: <20250422192819.302784-96-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé All targets have been converted to TCGCPUOps::mmu_index(), remove the now unused CPUClass::mmu_index(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-24-philmd@linaro.org> --- include/accel/tcg/cpu-mmu-index.h | 4 +--- include/hw/core/cpu.h | 2 -- accel/tcg/cpu-exec.c | 1 + 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/include/accel/tcg/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-index.h index f1ca385d3c..e681a90844 100644 --- a/include/accel/tcg/cpu-mmu-index.h +++ b/include/accel/tcg/cpu-mmu-index.h @@ -34,9 +34,7 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) # endif #endif - const TCGCPUOps *tcg_ops = cs->cc->tcg_ops; - int ret = tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch) - : cs->cc->mmu_index(cs, ifetch); + int ret = cs->cc->tcg_ops->mmu_index(cs, ifetch); tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); return ret; } diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 29f6419050..28bd27b8ed 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -104,7 +104,6 @@ struct SysemuCPUOps; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @mmu_index: Callback for choosing softmmu mmu index. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: @@ -151,7 +150,6 @@ struct CPUClass { ObjectClass *(*class_by_name)(const char *cpu_model); void (*parse_features)(const char *typename, char *str, Error **errp); - int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, size_t len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 034c2ded6b..9e15105533 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1075,6 +1075,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_interrupt); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); + assert(tcg_ops->mmu_index); tcg_ops->initialize(); tcg_target_initialized = true; }