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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a06d4c5fc4sm1537508f8f.57.2025.04.24.02.47.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 02:47:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Cc: Pierrick Bouvier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 11/13] physmem: Restrict TCG IOMMU code to TCG accel Date: Thu, 24 Apr 2025 11:46:51 +0200 Message-ID: <20250424094653.35932-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424094653.35932-1-philmd@linaro.org> References: <20250424094653.35932-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Restrict iotlb_to_section(), address_space_translate_for_iotlb() and memory_region_section_get_iotlb() to TCG. Declare them in the new "accel/tcg/iommu.h" header. Declare iotlb_to_section() using the MemoryRegionSection typedef. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- include/accel/tcg/iommu.h | 41 +++++++++++++++++++++++++++++++++++++++ include/exec/exec-all.h | 26 ------------------------- accel/tcg/cputlb.c | 1 + system/physmem.c | 5 +++++ 5 files changed, 48 insertions(+), 27 deletions(-) create mode 100644 include/accel/tcg/iommu.h diff --git a/MAINTAINERS b/MAINTAINERS index 661a47db5ac..3a37cc73af7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -168,7 +168,7 @@ F: include/exec/helper*.h.inc F: include/exec/helper-info.c.inc F: include/exec/page-protection.h F: include/system/tcg.h -F: include/accel/tcg/cpu-ops.h +F: include/accel/tcg/ F: host/include/*/host/cpuinfo.h F: util/cpuinfo-*.c F: include/tcg/ diff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h new file mode 100644 index 00000000000..90cfd6c0ed1 --- /dev/null +++ b/include/accel/tcg/iommu.h @@ -0,0 +1,41 @@ +/* + * TCG IOMMU translations. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef ACCEL_TCG_IOMMU_H +#define ACCEL_TCG_IOMMU_H + +#ifdef CONFIG_USER_ONLY +#error Cannot include accel/tcg/iommu.h from user emulation +#endif + +#include "exec/hwaddr.h" +#include "exec/memattrs.h" + +/** + * iotlb_to_section: + * @cpu: CPU performing the access + * @index: TCG CPU IOTLB entry + * + * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that + * it refers to. @index will have been initially created and returned + * by memory_region_section_get_iotlb(). + */ +MemoryRegionSection *iotlb_to_section(CPUState *cpu, + hwaddr index, MemTxAttrs attrs); + +MemoryRegionSection *address_space_translate_for_iotlb(CPUState *cpu, + int asidx, + hwaddr addr, + hwaddr *xlat, + hwaddr *plen, + MemTxAttrs attrs, + int *prot); + +hwaddr memory_region_section_get_iotlb(CPUState *cpu, + MemoryRegionSection *section); + +#endif + diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 816274bf905..b9eb9bc4b63 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -21,7 +21,6 @@ #define EXEC_ALL_H #include "exec/hwaddr.h" -#include "exec/memattrs.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" @@ -121,29 +120,4 @@ int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, #endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ -#if !defined(CONFIG_USER_ONLY) - -/** - * iotlb_to_section: - * @cpu: CPU performing the access - * @index: TCG CPU IOTLB entry - * - * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that - * it refers to. @index will have been initially created and returned - * by memory_region_section_get_iotlb(). - */ -struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, - hwaddr index, MemTxAttrs attrs); -#endif - -#if !defined(CONFIG_USER_ONLY) - -MemoryRegionSection * -address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, - hwaddr *xlat, hwaddr *plen, - MemTxAttrs attrs, int *prot); -hwaddr memory_region_section_get_iotlb(CPUState *cpu, - MemoryRegionSection *section); -#endif - #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ca69128232c..d11989f5674 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/iommu.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "system/memory.h" diff --git a/system/physmem.c b/system/physmem.c index ccbeae241c4..f1ec0902c78 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -29,6 +29,7 @@ #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/iommu.h" #endif /* CONFIG_TCG */ #include "exec/exec-all.h" @@ -587,6 +588,8 @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, return mr; } +#ifdef CONFIG_TCG + typedef struct TCGIOMMUNotifier { IOMMUNotifier n; MemoryRegion *mr; @@ -771,6 +774,8 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, return section - d->map.sections; } +#endif /* CONFIG_TCG */ + void cpu_address_space_init(CPUState *cpu, int asidx, const char *prefix, MemoryRegion *mr) {