From patchwork Thu May 1 21:04:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 886383 Delivered-To: patch@linaro.org Received: by 2002:a5d:430f:0:b0:38f:210b:807b with SMTP id h15csp515620wrq; Thu, 1 May 2025 14:11:00 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWZAO8HZJsr1MhvnmgLp8jmYWK1+dVp1Va4baLntcF8sxHu3e6pYSNa/GUJrkGmVU//IjT6Lg==@linaro.org X-Google-Smtp-Source: AGHT+IEmd2knclYXefQZpALPggr5m2aXORmhx6ZrSD61gi1jhkWABvjdwVmz1El1eHI7xmlQ5NmI X-Received: by 2002:a05:622a:4005:b0:476:bb8e:a90e with SMTP id d75a77b69052e-48c3173799fmr9080921cf.20.1746133860580; Thu, 01 May 2025 14:11:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746133860; cv=none; d=google.com; s=arc-20240605; b=R9KbxgkW4bOFnoKZaAMhowTaBHrHk28w4GPJ0bMCAFZXXXgfcQT1JqrqzdRCTka7TX RTT+f4hov5QH1Pzq6gNB3Hjsz2vRyfiq+aEE/Uaz1LlHlTRb27kgLe/+e7wgQbTg5+Jq Yfwi1aeTJav4Mg8mAYmyYvVz+1Q/eroQ5uoI8wwZNTyrYMO/vY1dawl4FzlUhNfqzH5k JB4N1IDqdvcPHi50yBQZa0bxrFH/MmuK/z9tSt/0MpQaiGhp+z3jTai9IQ93KmHqsSfk urb81E9d6oiP9MuqhOXtfpCz6XjR2LkcpipYih2KkhDIQmQOk4UVcD3IWyWtWaw/pAj8 1fyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Vdzft+xCucigY9en84sWDKvV9F8XabM3RidQg1HEXDs=; fh=uloqeIiLIhsqAWHY8zIEmzfMIcw7bGWZuINspytDykk=; b=j60VJoIWuRRg4w0bG+iq9fEnitMwgP1XlkJNHN3DzuCZcYDx4+TZs8tHMxh7cgzY4R MqG94eRI89pkNXU9nmiL6CQxeSkPR342RwWOPb7GkGSno/kqhUnueKmCa274+ICn9iIe srnZZ1x90X5+KIvhr1KiQTjA0iz2Bsi0wcQ+W3XhD5Y6Nkd40A4Gow86XeeH6vW2fcic XSknH9URmEuI+dl5wmQkcoFuop7CzeaUQkvI4P/Vn6aKs7oMJ1/1EqC4cQOaYWJN4Mf/ 7NQKJo+5hzKtJradrtytUiEHiJq1VOlfnaFBez6F3d6JtQUe6lEGncFlOHDhW1i7dIt+ Mw3Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IgqS5vbT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-48b98246ba5si13946621cf.329.2025.05.01.14.11.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 May 2025 14:11:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IgqS5vbT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAbAj-0007PB-Ap; Thu, 01 May 2025 17:10:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAb89-0004I5-QW for qemu-devel@nongnu.org; Thu, 01 May 2025 17:07:47 -0400 Received: from mail-il1-x12e.google.com ([2607:f8b0:4864:20::12e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAb88-0006sc-35 for qemu-devel@nongnu.org; Thu, 01 May 2025 17:07:41 -0400 Received: by mail-il1-x12e.google.com with SMTP id e9e14a558f8ab-3d93deba52fso4621585ab.0 for ; Thu, 01 May 2025 14:07:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746133659; x=1746738459; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vdzft+xCucigY9en84sWDKvV9F8XabM3RidQg1HEXDs=; b=IgqS5vbT09UI6H6Lf6GSYXrxHx+96pcdd5SeJBGp9+77qxK2U+fKmdCniViQ11h/mr E3Mb3wD5AzjGx11NpwVGDpmvdqeSpd2SPcI06sq2Sw5T6MnJTARbKTuYjPLdi5d6Gtas EkHBdKdv0aCVOIZl6XuMFHpk0J8nIyHdCFEZagm41yCBBPd6E76cUAmciSTwELhZDzAs Jpm20kt6dUUQRjt/r+WbgzVQZj2obSS5L1RAJOAsJPgkUZu0nuI37gxw+VtgsGuReww7 Fvz9UV0FB/HMr3oJ0CnySA5Rsp80DtCHCL/KnFxrxDafgCw3a6AM/i3KCRa/X0vsIQIM PZkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746133659; x=1746738459; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vdzft+xCucigY9en84sWDKvV9F8XabM3RidQg1HEXDs=; b=LB4YzLH9uKa4VTBu0CVTd3MtcuIMcmWU5yjjgp3+sa+4h7AgqEbv0Asf/BBGvxw6OC qV9rKDyoS+y43PeAWy/M+Jz4c0mPMzadkBffcU8U4Lr9lsa3XZ4wNTkPY0oAAQVTEUWG FVhQOlf7jS001gEgxNtwQ3M1zniXuIvM5M8SbajtMogDJGz6Dwul/zC1PW5MAYb5MLCl 6zaMrf7EBFGL/F/Q+3EZHsVxoL3MKvl9y/62dZ10Rng5E12KCBMcRWP5ALaQ21jpFK3d zwcEl55yXZVuRdauEujif2dfRPOf8Uuaon/Ge/kN3MQsHhG2hPP073N+0Wqk70ShUSRe w3JQ== X-Gm-Message-State: AOJu0YwwC3VNnPjJVd3Io/PdnDW3Oh58d4r4NyCjfEQ9vKUdULneEo7J DCW19YmKlA17+rivOBSR/lLhbaAWxfpvqHfIXNgYSXyNrmatWVm5ahyJrHp6NCcg5ya+GXUMyu5 5 X-Gm-Gg: ASbGncsbbtzuVa/RpjtmikCYzZNq5LHMZChAG30kCZrFVJcCp6Q8wS50lQOxluCkmxL d2jLS5u7lylWzhLxpS6Jdo46Q27PBgsDlLpeD5b/aaXO+6/r97KeugBpfVQbjYtYSWfZwnsHctN 6s8bdSD8TAJsUZ9Ywq5hoXiLuusA2vq7Nz9kPDCRbzgGKsy5/wGALHuaOIacezbc+IJxp0aNm0Q JMjX5Ar9iNKwD2lmOf9UJ9hMf5bGKskp1C6f44D464ALGczhy8cA98jZDlD3A3hLvfXFbHZ5U9x ox1kvVP+sRV7WCxAh6P+LVzQUQvYxhBu/TDP0q6GpDSq3cq9RK51op7u2OK2ZtApBd/ghdNbLfS /PFidrzjk/WUZUltnA3wIClpVjw== X-Received: by 2002:a92:c24b:0:b0:3d4:337f:121c with SMTP id e9e14a558f8ab-3d97c182360mr6369495ab.10.1746133658742; Thu, 01 May 2025 14:07:38 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4f88a9140e2sm49190173.37.2025.05.01.14.07.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 01 May 2025 14:07:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Cl=C3=A9ment_Mathieu--Drif?= , Zhao Liu , Hanna Reitz , Igor Mammedov , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Paolo Bonzini , Eduardo Habkost , qemu-block@nongnu.org, Jason Wang , Richard Henderson , Yanan Wang , Ani Sinha , "Michael S. Tsirkin" , Thomas Huth , Gerd Hoffmann , Kevin Wolf , Yi Liu Subject: [PATCH 18/18] hw/i386/x86-iommu: Remove X86IOMMUState::pt_supported field Date: Thu, 1 May 2025 23:04:56 +0200 Message-ID: <20250501210456.89071-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250501210456.89071-1-philmd@linaro.org> References: <20250501210456.89071-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12e; envelope-from=philmd@linaro.org; helo=mail-il1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The X86IOMMUState::pt_supported boolean was only set in the hw_compat_2_9[] array, via the 'pt=off' property. We removed all machines using that array, lets remove that property and all the code around it, always setting the VTD_ECAP_PT capability. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i386/x86-iommu.h | 1 - hw/i386/amd_iommu.c | 12 ++---------- hw/i386/intel_iommu.c | 13 ++----------- hw/i386/x86-iommu.c | 1 - 4 files changed, 4 insertions(+), 23 deletions(-) diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h index bfd21649d08..d6e52b1eb6b 100644 --- a/include/hw/i386/x86-iommu.h +++ b/include/hw/i386/x86-iommu.h @@ -63,7 +63,6 @@ struct X86IOMMUState { SysBusDevice busdev; OnOffAuto intr_supported; /* Whether vIOMMU supports IR */ bool dt_supported; /* Whether vIOMMU supports DT */ - bool pt_supported; /* Whether vIOMMU supports pass-through */ QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */ }; diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 2cf7e24a21d..516e231bf13 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1426,7 +1426,6 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) AMDVIState *s = opaque; AMDVIAddressSpace **iommu_as, *amdvi_dev_as; int bus_num = pci_bus_num(bus); - X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); iommu_as = s->address_spaces[bus_num]; @@ -1486,15 +1485,8 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) AMDVI_INT_ADDR_FIRST, &amdvi_dev_as->iommu_ir, 1); - if (!x86_iommu->pt_supported) { - memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); - memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), - true); - } else { - memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), - false); - memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, true); - } + memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); + memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), true); } return &iommu_as[devfn]->as; } diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c980cecb4ee..cc08dc41441 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1066,6 +1066,7 @@ static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu, { switch (vtd_ce_get_type(ce)) { case VTD_CONTEXT_TT_MULTI_LEVEL: + case VTD_CONTEXT_TT_PASS_THROUGH: /* Always supported */ break; case VTD_CONTEXT_TT_DEV_IOTLB: @@ -1074,12 +1075,6 @@ static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu, return false; } break; - case VTD_CONTEXT_TT_PASS_THROUGH: - if (!x86_iommu->pt_supported) { - error_report_once("%s: PT specified but not supported", __func__); - return false; - } - break; default: /* Unknown type */ error_report_once("%s: unknown ce type: %"PRIu32, __func__, @@ -4520,7 +4515,7 @@ static void vtd_cap_init(IntelIOMMUState *s) { X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); - s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | + s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_ECAP_PT | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | VTD_CAP_MGAW(s->aw_bits); if (s->dma_drain) { @@ -4548,10 +4543,6 @@ static void vtd_cap_init(IntelIOMMUState *s) s->ecap |= VTD_ECAP_DT; } - if (x86_iommu->pt_supported) { - s->ecap |= VTD_ECAP_PT; - } - if (s->caching_mode) { s->cap |= VTD_CAP_CM; } diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index d34a6849f4a..ca7cd953e98 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -129,7 +129,6 @@ static const Property x86_iommu_properties[] = { DEFINE_PROP_ON_OFF_AUTO("intremap", X86IOMMUState, intr_supported, ON_OFF_AUTO_AUTO), DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false), - DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true), }; static void x86_iommu_class_init(ObjectClass *klass, const void *data)