diff mbox series

[PULL,09/59] accel/tcg: Simplify L1_MAP_ADDR_SPACE_BITS

Message ID	20250501212113.2961531-10-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: Pierrick Bouvier <pierrick.bouvier@linaro.org> Subject: [PULL 09/59] accel/tcg: Simplify L1_MAP_ADDR_SPACE_BITS Date: Thu, 1 May 2025 14:20:23 -0700 Message-ID: <20250501212113.2961531-10-richard.henderson@linaro.org> In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/59] accel/tcg: Add CPUState argument to page_unprotect \| expand [PULL,01/59] accel/tcg: Add CPUState argument to page_unprotect [PULL,02/59] accel/tcg: Add CPUState argument to tb_invalidate_phys_page_unwind [PULL,03/59] accel/tcg: Add CPUState arg to tb_invalidate_phys_page_range__locked [PULL,04/59] accel/tcg: Merge tb_invalidate_phys_range{__locked} [PULL,05/59] accel/tcg: Add CPUState arg to tb_invalidate_phys_range [PULL,06/59] accel/tcg: Add CPUState arg to tb_invalidate_phys_range_fast [PULL,07/59] accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc [PULL,08/59] accel/tcg: Simplify CPU_TLB_DYN_MAX_BITS [PULL,09/59] accel/tcg: Simplify L1_MAP_ADDR_SPACE_BITS [PULL,10/59] accel/tcg: Merge internal-target.h into internal-common.h [PULL,11/59] accel/tcg: Reduce scope of tb_phys_invalidate, tb_set_jmp_target [PULL,12/59] accel/tcg: Use vaddr for walk_memory_regions callback [PULL,13/59] accel/tcg: Use vaddr in user/page-protection.h [PULL,14/59] include/exec: Include missing headers in exec-all.h [PULL,15/59] include/exec: Move tb_invalidate_phys_range to translation-block.h [PULL,16/59] accel/tcg: Compile tb-maint.c twice [PULL,17/59] accel/tcg: Remove #error for non-tcg in getpc.h [PULL,18/59] target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c [PULL,19/59] accel/tcg: Include 'accel/tcg/getpc.h' in 'exec/helper-proto' [PULL,20/59] physmem: Move TCG IOTLB methods around [PULL,21/59] physmem: Restrict TCG IOTLB code to TCG accel [PULL,22/59] accel/tcg: Extract probe API out of 'exec/exec-all.h' [PULL,23/59] include: Remove 'exec/exec-all.h' [PULL,24/59] accel/tcg: Generalize fake_user_interrupt test [PULL,25/59] accel/tcg: Unconditionally use CPU_DUMP_CCOP in log_cpu_exec [PULL,26/59] accel/tcg: Introduce TCGCPUOps.cpu_exec_reset [PULL,27/59] target/i386: Split out x86_cpu_exec_reset [PULL,28/59] accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.h [PULL,29/59] target/arm: Move cpu_get_tb_cpu_state to hflags.c [PULL,30/59] target/arm: Unexport assert_hflags_rebuild_correctly [PULL,31/59] target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.c [PULL,32/59] accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state [PULL,33/59] accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps [PULL,34/59] accel/tcg: Pass TCGTBCPUState to tb_lookup [PULL,35/59] accel/tcg: Pass TCGTBCPUState to tb_htable_lookup [PULL,36/59] accel/tcg: Use TCGTBCPUState in struct tb_desc [PULL,37/59] accel/tcg: Pass TCGTBCPUState to tb_gen_code [PULL,38/59] accel/tcg: Split out accel/tcg/helper-retaddr.h [PULL,39/59] accel/tcg: Compile cpu-exec.c twice [PULL,40/59] system/vl: Filter machine list available for a particular target binary [PULL,41/59] qemu/target_info: Add %target_cpu_type field to TargetInfo [PULL,42/59] qemu: Introduce target_long_bits() [PULL,43/59] tcg: Define INSN_START_WORDS as constant 3 [PULL,44/59] accel/tcg: Don't use TARGET_LONG_BITS in decode_sleb128 [PULL,45/59] accel/tcg: Use target_long_bits() in translate-all.c [PULL,46/59] accel/tcg: Build translate-all.c twice [PULL,47/59] accel/tcg: Build tcg-all.c twice [PULL,48/59] accel/tcg: Use vaddr in cpu_loop.h [PULL,49/59] accel/tcg: Move user-only tlb_vaddr_to_host out of line [PULL,50/59] accel/tcg: Move tlb_vaddr_to_host declaration to probe.h [PULL,51/59] accel/tcg: Use target_long_bits() in cputlb.c [PULL,52/59] accel/tcg: Use vaddr for plugin_{load,store}_cb [PULL,53/59] accel/tcg: Build cputlb.c once [PULL,54/59] include/user: Convert GUEST_ADDR_MAX to a variable [PULL,55/59] include/user: Use vaddr in guest-host.h [PULL,56/59] accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addr [PULL,57/59] accel/tcg: Remove TARGET_PAGE_DATA_SIZE [PULL,58/59] accel/tcg: Avoid abi_ptr in user-exec.c [PULL,59/59] accel/tcg: Build user-exec.c once

Commit Message

Richard Henderson May 1, 2025, 9:20 p.m. UTC

Stop taking TARGET_PHYS_ADDR_SPACE_BITS into account.
Simply allow the entire ram_addr_t space.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/tb-maint.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff mbox series

Patch

diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c
index 1596767879..13d0376bc7 100644
--- a/accel/tcg/tb-maint.c
+++ b/accel/tcg/tb-maint.c
@@ -160,11 +160,7 @@  static PageForEachNext foreach_tb_next(PageForEachNext tb,
 /*
  * In system mode we want L1_MAP to be based on ram offsets.
  */
-#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
-# define L1_MAP_ADDR_SPACE_BITS  HOST_LONG_BITS
-#else
-# define L1_MAP_ADDR_SPACE_BITS  TARGET_PHYS_ADDR_SPACE_BITS
-#endif
+#define L1_MAP_ADDR_SPACE_BITS  HOST_LONG_BITS
 
 /* Size of the L2 (and L3, etc) page tables.  */
 #define V_L2_BITS 10