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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-740590610desm135897b3a.146.2025.05.01.14.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 May 2025 14:24:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 42/59] qemu: Introduce target_long_bits() Date: Thu, 1 May 2025 14:20:56 -0700 Message-ID: <20250501212113.2961531-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250501212113.2961531-1-richard.henderson@linaro.org> References: <20250501212113.2961531-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/target-info-impl.h | 2 ++ include/qemu/target-info.h | 7 +++++++ target-info-stub.c | 1 + target-info.c | 5 +++++ 4 files changed, 15 insertions(+) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h index 76766eeaae..1b51cbcfe1 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -14,6 +14,8 @@ typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *target_name; + /* runtime equivalent of TARGET_LONG_BITS definition */ + unsigned long_bits; /* runtime equivalent of CPU_RESOLVING_TYPE definition */ const char *cpu_type; /* QOM typename machines for this binary must implement */ diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 2b6ccabb11..850a2958b9 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -16,6 +16,13 @@ */ const char *target_name(void); +/** + * target_long_bits: + * + * Returns: number of bits in a long type for this target (i.e. 64). + */ +unsigned target_long_bits(void); + /** * target_machine_typename: * diff --git a/target-info-stub.c b/target-info-stub.c index 86da297277..fecc0e7128 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -14,6 +14,7 @@ static const TargetInfo target_info_stub = { .target_name = TARGET_NAME, + .long_bits = TARGET_LONG_BITS, .cpu_type = CPU_RESOLVING_TYPE, .machine_typename = TYPE_MACHINE, }; diff --git a/target-info.c b/target-info.c index 5f5ef1f932..16fdca7aaa 100644 --- a/target-info.c +++ b/target-info.c @@ -15,6 +15,11 @@ const char *target_name(void) return target_info()->target_name; } +unsigned target_long_bits(void) +{ + return target_info()->long_bits; +} + const char *target_cpu_type(void) { return target_info()->cpu_type;