Message ID | 20250506144214.1221450-28-peter.maydell@linaro.org |
---|---|
State | New |
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[PULL,01/32] hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC
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diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index b4bff145794..f6e49ce9b8d 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -348,14 +348,14 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, case DESIGNWARE_PCIE_ATU_LOWER_BASE: case DESIGNWARE_PCIE_ATU_UPPER_BASE: - viewport->base = deposit64(root->msi.base, + viewport->base = deposit64(viewport->base, address == DESIGNWARE_PCIE_ATU_LOWER_BASE ? 0 : 32, 32, val); break; case DESIGNWARE_PCIE_ATU_LOWER_TARGET: case DESIGNWARE_PCIE_ATU_UPPER_TARGET: - viewport->target = deposit64(root->msi.base, + viewport->target = deposit64(viewport->target, address == DESIGNWARE_PCIE_ATU_LOWER_TARGET ? 0 : 32, 32, val); break;