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[PULL,05/32] target/arm/ptw: get current security_space for current mmu_idx

Message ID 20250506144214.1221450-6-peter.maydell@linaro.org
State New
Headers show
Series [PULL,01/32] hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC | expand

Commit Message

Peter Maydell May 6, 2025, 2:41 p.m. UTC 
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>

It should be equivalent to previous code.
Allow to call common function to get a page address later.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20250414153027.1486719-3-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index bdb4de7c047..0ae9c5a3f49 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3636,7 +3636,7 @@  hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
     ARMMMUIdx mmu_idx = arm_mmu_idx(env);
-    ARMSecuritySpace ss = arm_security_space(env);
+    ARMSecuritySpace ss = arm_mmu_idx_to_security_space(env, mmu_idx);
     S1Translate ptw = {
         .in_mmu_idx = mmu_idx,
         .in_space = ss,