From patchwork Wed May 7 23:41:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pierrick Bouvier X-Patchwork-Id: 888138 Delivered-To: patch@linaro.org Received: by 2002:a5d:4683:0:b0:38f:210b:807b with SMTP id u3csp632837wrq; Wed, 7 May 2025 16:45:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXdDkgyYPLfVY4t+rllQ+2g6xfdQwweILaCAiKgskMStT10AGvwVWm3BFlGsSA+sDVOI9cHow==@linaro.org X-Google-Smtp-Source: AGHT+IG5+CtJBV52fSkzCj0+6dhWCR7dvAh7oPYsedvXtt4ezNfEI0txZyVtuc/cWAZTmVAHkqnI X-Received: by 2002:ad4:594f:0:b0:6d4:1425:6d2d with SMTP id 6a1803df08f44-6f542afacf1mr86862126d6.43.1746661549971; Wed, 07 May 2025 16:45:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746661549; cv=none; d=google.com; s=arc-20240605; b=iOmIrbhb/hunQvynpamq5QCrI2vPq3GPIlw1WVHo5SZDkV+ATqZEnY8gXxkRlE9+cq NDhCdimrexmKJFBmNxz9HWzf/OgwZVmlAxQu4Pu8CFKfJZJZHdeqA5odRkVANJkM7CjT KCclLH2HcMoJRy1R+bnLHb1PaPsyr/0a4mmFQxyMGXUD+gb7D8STTxj5vhCVR3I4c7Mr LwbCOV6SbfeqtcnEHz+VZIwSPaAsvoLh0g0o4/XdFVHmdpuOVPN5SfqbiMuOcPOdmLd4 bmWCmjaH4NN3DyzIlqIJkxHqgkUsP4+qknKjAIqNO2QyDZFmBoAZcNMvy0x3au7LF9O9 bDxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cH5ZtRCeVBPeaEwJ188gDPaPfkE7sAMWROIwRI8/rfo=; fh=Zbxy5TRiDd+Eff0zsN+2XmZYe/TihsWpxb97dHV4h78=; b=XGH3vTMyy22ruQAAVw1WrlTxchlTWFEt7Zelqvpa/rVucLdy1GqlNwg4RAmt1gQcWo DEeTZUZKeAEXdIQyYfJ4KsZZ6huwPr/pGsRs075yjyVW+qPQ8VW7IvqN9tBDFKfTjd5+ yhxoBorcbFPmNFF8QUNpcYRLS/CdYeDVgpPzlK2pyNVE2yi0wwajXKGKvSnh6xwViWoN 3w9IdAd0AAGZp19yjrFJdjlmdGXlJSpMV3+4DOyxF6HaTE4ebAYX23nC+T+YSaiXtAb1 VE4hjb5JPsfd/1GV7XIhsesls6HMAtjvX6QnPAvXqBBR9JNrYQ4vMKzCzcImNAl7SHYX 8jHA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WsYAm63W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6f54262712dsi31620236d6.29.2025.05.07.16.45.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 07 May 2025 16:45:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WsYAm63W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uCoPn-0008Qs-GX; Wed, 07 May 2025 19:43:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uCoPc-00087s-8F for qemu-devel@nongnu.org; Wed, 07 May 2025 19:42:55 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uCoPa-0002RK-1H for qemu-devel@nongnu.org; Wed, 07 May 2025 19:42:52 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-227d6b530d8so4593025ad.3 for ; Wed, 07 May 2025 16:42:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746661368; x=1747266168; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cH5ZtRCeVBPeaEwJ188gDPaPfkE7sAMWROIwRI8/rfo=; b=WsYAm63WuKJ52gNYt9q726MiToVodeiHtcotrz2vLOMYhht5oBGUs2e2w4CE3PimNN hqcmUP9SfonSPTZK+fg898StZD1ukqc+qkeRQ4UysRqkSyGYHcd4fzYuDaGnQOcxNYAS aLv15q9IwtoPX2BS0JURsd1jZPim6sKcR7Yt9z4EoVZTRbcnMawF13o5ETtIJsyBIe2F 8gGHwI+c7wr9PBHo1LrBBUH54iR7lpKD4X96c0+rsA8HfcltZ0tTxFdEN80q/LzcEqX5 gvisHu6P6hFdJ3A4fdBqM7s0y2F99Jkb5m/T/3hG3Ie2nXyzwrgblGxs/r5Ik10G+pH+ zr6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746661368; x=1747266168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cH5ZtRCeVBPeaEwJ188gDPaPfkE7sAMWROIwRI8/rfo=; b=TJUhJyZa9aBLyyn+yYh7Re7kCnEGmynU9wy3gVyPEcpK6xh1iLuEEcTg2MU2g9lett GYJd7SXjTVe/sbxSUmIwyUDXiM/3aphyL1bQkJzutplSXpa/DL9qx9BZLQlOiKp5meU0 jO1wRTiztBdOy7+Z4QNJZEzUYZQ4kgSYsQS1w2hJq5vK/6MgDKyV6ykxAy6+zBKWGhqm +Kb4Ifpxr/iivPZPL7fKXE7AtbdEoeXmQ+/0PX8ZVyCCCcYu6ZKm0rwIToxWySZhR2iw jgEYi707YwYTadi0s2oxcQw0CNHKpyP7yEgpLXBoO22T3j5wdEQB/h1Iv88SVWEU9z3u OMQg== X-Gm-Message-State: AOJu0YwyKW4q9T39VdCcXAsmW4lyoTrqQtOs8P/RKwnfapcclXq5sMok 2NamFX1JdxhZCoe9wcQL57z28j6VwU+u7LN0j9thU7Kh5cQkJTKh0jJ+07Z8lcfN+i1q9qn8lFB LfmuK6A== X-Gm-Gg: ASbGncu3xuLxrTMfKnF7gOQ3BLba8PMIBoCH+m5zjgP32fmgTcw3MbeFvqmrTxtWQwI UDl2A8+TOxHzykZFlxV8s9s/lqVFbXZdt9HImrIV8dTgF3UAFIU830sYPDukw9yHSyb815Hsb/8 WOQIk1ENt2OfnymYhMpfVDvWecURcxNyj4kpOQXAAYJJjUGpYifWQOFexp/fg+aYiIeKprc2lyg SXjoXwId56fG9ubWorHlMQ9OIXWGK2xNqIluzUZxEhYtvqNH/E0JiErFx9K4cZHolS3ijjDOYos EQtl7w/F/k5Qa9ufFuq4CF6G+liT7wkvBEuvpd26 X-Received: by 2002:a17:902:d50f:b0:220:c911:3f60 with SMTP id d9443c01a7336-22e5ee1cc66mr81484075ad.47.1746661368656; Wed, 07 May 2025 16:42:48 -0700 (PDT) Received: from pc.. ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e815806fdsm6491325ad.17.2025.05.07.16.42.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 May 2025 16:42:48 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, anjo@rev.ng, Peter Maydell , Richard Henderson , alex.bennee@linaro.org, Paolo Bonzini , kvm@vger.kernel.org, =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v7 06/49] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Date: Wed, 7 May 2025 16:41:57 -0700 Message-ID: <20250507234241.957746-7-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250507234241.957746-1-pierrick.bouvier@linaro.org> References: <20250507234241.957746-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Allow to get rid of CONFIG_KVM in target/arm/cpu.c Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Pierrick Bouvier --- target/arm/kvm_arm.h | 2 ++ target/arm/cpu.c | 31 ------------------------------- target/arm/kvm-stub.c | 5 +++++ target/arm/kvm.c | 29 +++++++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 31 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 5bf5d56648f..b638e09a687 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -216,4 +216,6 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); void kvm_arm_enable_mte(Object *cpuobj, Error **errp); +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 45cb6fd7eed..d062829ec14 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1098,37 +1098,6 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) } } -static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) -{ -#ifdef CONFIG_KVM - ARMCPU *cpu = opaque; - CPUARMState *env = &cpu->env; - CPUState *cs = CPU(cpu); - uint32_t linestate_bit; - int irq_id; - - switch (irq) { - case ARM_CPU_IRQ: - irq_id = KVM_ARM_IRQ_CPU_IRQ; - linestate_bit = CPU_INTERRUPT_HARD; - break; - case ARM_CPU_FIQ: - irq_id = KVM_ARM_IRQ_CPU_FIQ; - linestate_bit = CPU_INTERRUPT_FIQ; - break; - default: - g_assert_not_reached(); - } - - if (level) { - env->irq_line_state |= linestate_bit; - } else { - env->irq_line_state &= ~linestate_bit; - } - kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); -#endif -} - static bool arm_cpu_virtio_is_big_endian(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index e34d3f5e6b4..4806365cdc5 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -104,3 +104,8 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) { g_assert_not_reached(); } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9c62d12b233..b6c39ca61fa 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2429,3 +2429,32 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp) cpu->kvm_mte = true; } } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + ARMCPU *cpu = arm_cpu; + CPUARMState *env = &cpu->env; + CPUState *cs = CPU(cpu); + uint32_t linestate_bit; + int irq_id; + + switch (irq) { + case ARM_CPU_IRQ: + irq_id = KVM_ARM_IRQ_CPU_IRQ; + linestate_bit = CPU_INTERRUPT_HARD; + break; + case ARM_CPU_FIQ: + irq_id = KVM_ARM_IRQ_CPU_FIQ; + linestate_bit = CPU_INTERRUPT_FIQ; + break; + default: + g_assert_not_reached(); + } + + if (level) { + env->irq_line_state |= linestate_bit; + } else { + env->irq_line_state &= ~linestate_bit; + } + kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); +}