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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fbd4474c1sm3299195ad.112.2025.05.08.06.40.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 08 May 2025 06:40:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Sergio Lopez , Gerd Hoffmann , Peter Maydell , Laurent Vivier , Jiaxun Yang , Yi Liu , "Michael S. Tsirkin" , Eduardo Habkost , Marcel Apfelbaum , Alistair Francis , Daniel Henrique Barboza , Marcelo Tosatti , qemu-riscv@nongnu.org, Weiwei Li , Amit Shah , Zhao Liu , Yanan Wang , Helge Deller , Palmer Dabbelt , Ani Sinha , Igor Mammedov , Fabiano Rosas , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Liu Zhiwei , =?utf-8?q?Cl=C3=A9ment_Mathieu--?= =?utf-8?q?Drif?= , qemu-arm@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Huacai Chen , Jason Wang Subject: [PATCH v4 12/27] target/i386/cpu: Remove CPUX86State::enable_cpuid_0xb field Date: Thu, 8 May 2025 15:35:35 +0200 Message-ID: <20250508133550.81391-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250508133550.81391-1-philmd@linaro.org> References: <20250508133550.81391-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The CPUX86State::enable_cpuid_0xb boolean was only disabled for the pc-q35-2.6 and pc-i440fx-2.6 machines, which got removed. Being now always %true, we can remove it and simplify cpu_x86_cpuid(). Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.h | 3 --- target/i386/cpu.c | 6 ------ 2 files changed, 9 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0db70a70439..06817a31cf9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2241,9 +2241,6 @@ struct ArchCPU { */ bool legacy_multi_node; - /* Compatibility bits for old machine types: */ - bool enable_cpuid_0xb; - /* Enable auto level-increase for all CPUID leaves */ bool full_cpuid_auto_level; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 49179f35812..6fe37f71b1e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6982,11 +6982,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0xB: /* Extended Topology Enumeration Leaf */ - if (!cpu->enable_cpuid_0xb) { - *eax = *ebx = *ecx = *edx = 0; - break; - } - *ecx = count & 0xff; *edx = cpu->apic_id; @@ -8828,7 +8823,6 @@ static const Property x86_cpu_properties[] = { DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), - DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),