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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e150eb5d2sm112359365ad.7.2025.05.08.06.40.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 08 May 2025 06:40:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Sergio Lopez , Gerd Hoffmann , Peter Maydell , Laurent Vivier , Jiaxun Yang , Yi Liu , "Michael S. Tsirkin" , Eduardo Habkost , Marcel Apfelbaum , Alistair Francis , Daniel Henrique Barboza , Marcelo Tosatti , qemu-riscv@nongnu.org, Weiwei Li , Amit Shah , Zhao Liu , Yanan Wang , Helge Deller , Palmer Dabbelt , Ani Sinha , Igor Mammedov , Fabiano Rosas , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Liu Zhiwei , =?utf-8?q?Cl=C3=A9ment_Mathieu--?= =?utf-8?q?Drif?= , qemu-arm@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Huacai Chen , Jason Wang Subject: [PATCH v4 13/27] target/i386/cpu: Remove CPUX86State::fill_mtrr_mask field Date: Thu, 8 May 2025 15:35:36 +0200 Message-ID: <20250508133550.81391-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250508133550.81391-1-philmd@linaro.org> References: <20250508133550.81391-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The CPUX86State::fill_mtrr_mask boolean was only disabled for the pc-q35-2.6 and pc-i440fx-2.6 machines, which got removed. Being now always %true, we can remove it and simplify kvm_get_msrs(). Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.h | 3 --- target/i386/cpu.c | 1 - target/i386/kvm/kvm.c | 10 +++------- 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 06817a31cf9..7585407da54 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2253,9 +2253,6 @@ struct ArchCPU { /* Enable auto level-increase for Intel Processor Trace leave */ bool intel_pt_auto_level; - /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ - bool fill_mtrr_mask; - /* if true override the phys_bits value with a value read from the host */ bool host_phys_bits; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6fe37f71b1e..fb505d13122 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8810,7 +8810,6 @@ static const Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), - DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, UINT32_MAX), DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index c9a3c02e3e3..87edce99e85 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4635,13 +4635,9 @@ static int kvm_get_msrs(X86CPU *cpu) * we're migrating to. */ - if (cpu->fill_mtrr_mask) { - QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); - assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); - mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); - } else { - mtrr_top_bits = 0; - } + QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); + assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); + mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); for (i = 0; i < ret; i++) { uint32_t index = msrs[i].index;