From patchwork Thu May 8 13:35:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 888590 Delivered-To: patch@linaro.org Received: by 2002:adf:b60d:0:b0:3a1:f579:ae88 with SMTP id f13csp7449wre; Thu, 8 May 2025 06:39:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXLuMxB03TopcBCAfOFvSt27O8uBh6h95tr3++mzaKkhJlRS/ifzesD3w3mZzUFi2ZUmbjcpg==@linaro.org X-Google-Smtp-Source: AGHT+IEHFyOGuzmDdqf7/iRI7EWQZBuOoBVeawvDEWBo+L5SOTKQLljJGlF5qbgIlnQ+v/ATG8F9 X-Received: by 2002:a05:622a:11cf:b0:47b:3a2:ff22 with SMTP id d75a77b69052e-492265ebbe8mr100520341cf.29.1746711562080; Thu, 08 May 2025 06:39:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1746711562; cv=none; d=google.com; s=arc-20240605; b=OwEKBDqBBJuj0TcSrDrK5CZ/Bb/7q6V4RMpEPuGYLyspaMXOrOGZetQXibWSUbej2B ss/dl6Si2udcEjCOxG6baL+A2h5e1XhpAVThqlIwiJ9FDcJv5RgACU/jzVBKFjqW+jw/ XHhZ3tkUGevcZD4WgX2FpLqSNk1nxTOJOqKUanvIvcQZmczXdxwR0rshAQiYFnNaxoyn 9v0Ww9MYoQfEASUOisVq44CZx9PW95liKr6El0y6JoTZEPom//q1uESwQvffAA0nm7wz 6+E9eime4Cmse8QoPHHgGMYqRByWSfrHWjZ0exmUd6RRVtraSKIjxjNQ2lOHB9wQy5xb cspQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wpFm28NPDHDVh+ccZL7bpwZ5qyD7oJMGgna414/IiOE=; fh=t4sCPXSJJxzszaJF+1Mm6mpQfCAwhf2cujSX+L6g5pY=; b=BlIphBFH0xjLppKl91QzjYoTwYSUw75qIZ7oLkP+1PKHBoNojr2b/mTCq92rNasEm/ XA7KW1SUCcQ5tUNRVoyRWKiX8fzGAB8dc96Za2cnBI6Ftu/gKpuYsPr8LYx8do4iwNhg kBgzBBvMKLMc4u3iZfeACWsWQ/vAD7qNunZkwofuPQCwFOgJ8fQoXim65WnkJesO3P9m 5PL3lfNf6sHDwNYPovQeDatGFddQr8oIe9Z0AfGWfFsqrsFX+qgtKKFTwFt2fCuYGPIs Vu2FaKvykyldQwG7AXWg8rn3UDkOys2mFjxXZjymWpFXSCEBDhlYLSQvvu3dJsh7s2Sk svQg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dxa9saRt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-49222f8af9fsi46341471cf.467.2025.05.08.06.39.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 May 2025 06:39:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dxa9saRt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uD1Si-0001Hq-Jz; Thu, 08 May 2025 09:38:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uD1SD-0000Wz-E7 for qemu-devel@nongnu.org; Thu, 08 May 2025 09:38:30 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uD1S9-0003sU-Qm for qemu-devel@nongnu.org; Thu, 08 May 2025 09:38:24 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-22e5df32197so10935615ad.0 for ; Thu, 08 May 2025 06:38:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746711500; x=1747316300; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wpFm28NPDHDVh+ccZL7bpwZ5qyD7oJMGgna414/IiOE=; b=dxa9saRtQ5WgUstWpDY6Qkt9Fpayc5ysgWzHsFIc7v6mRvw7DuNifaIWStnh1l27Wt SMsDwtWpKPk1CIxTYRvU62hlZht2XD3FP9CgyTFM93eA+vzaTFjjzup1c6kSHwR+XJ7p ZPQavg8uj7J7Qmw0TRAM4tx/DXtBCsM5T7LVBnfUkACJkVNMAkBEMpBt1l7ndAzJXH9e 9isMl2Tnc+getmmKG4DyBMGxeMEvw9eZkHL64EbeQEm6UxYM/9AegEpO77rqUoiMeGUb IDk1zP2lk5o0Mycb160r7hyZtCEY0xeeEqlO4RQQR0mYLrrcC+HmqjLuceINK/E1IUjG Q+zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746711500; x=1747316300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wpFm28NPDHDVh+ccZL7bpwZ5qyD7oJMGgna414/IiOE=; b=XeVzMH53vjLURAaI8RRisdodg5+PJBYGAL2M9W+147vEf1dQ6s5BB8n9HBeSPGOcld z/yDFC4vJI2ENSL0XLlsBaYrtYjcHPkTf5PK2teTCAvBqH100ESX1w7/MN2KZ52WIg8B kQyujLjQf+NDt71Vg0z3q/wA5v2BrRLhSz7O8OcZd9vPq2Ub8mFHOccxG3TsKFbDhIVY rqnQ3/RIno+kglMZS0lzv/MUMXbLbU2iupKnJTfv1Qkn3allU2JxXnD6Srack5REL07a ImW6cEOuv+o6FcuAkGlFd0wqBmRr2tY0YyVwDOZkSWjOU5t8Fo6DhVZxni+DTYJmZIKG sx1w== X-Gm-Message-State: AOJu0YyQCxwTFUPzROD/VOHg4WW4/WXAponcw+pFAWc6KHOEcD61B4iC yfmXNvp0296Io9tML2RMvovLSGEQ8H6ICi5HjZRmsMRsvEU4slYtKplEx8x8gX0byuMdDHW6sdE yikqoyg== X-Gm-Gg: ASbGncu88qvVGDtDnRFligYpnzBH4XKTO5+nRodU0ht+b1XzcOmRsv9qZK5UlRnum0Q OMLtJOI4hQIqML7VCtMRrtdmS0amzr8rA3vk2sI5+tcgaDi0mQRDTqh6fGt3A037lBm8G2euRiI EqZT6lhHOxPPfD25E5QohBwyQGJ+w9kogpnfAIEmA8eNn4+m8bENwmqvJuGi1wutLR4ghSDsG20 JI7V6bDXclZ3w8a3YLC86xiijaeZN52XBwh+EXNgxHmCD1LY4HIfyffxBA0fawk+Fi9x3uOh2tu oGfi4npGyp2rC0Gkdz/jtSJx2u9573DpF540SqlLa4ei6inWJHDA2e/dj1U4FCjs8LfIq8TDNmm n35nHhYvvbJH9puc= X-Received: by 2002:a17:902:ecc6:b0:224:10a2:cae7 with SMTP id d9443c01a7336-22e5edf9e5cmr112894945ad.40.1746711499714; Thu, 08 May 2025 06:38:19 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e15232797sm112617585ad.240.2025.05.08.06.38.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 08 May 2025 06:38:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Sergio Lopez , Gerd Hoffmann , Peter Maydell , Laurent Vivier , Jiaxun Yang , Yi Liu , "Michael S. Tsirkin" , Eduardo Habkost , Marcel Apfelbaum , Alistair Francis , Daniel Henrique Barboza , Marcelo Tosatti , qemu-riscv@nongnu.org, Weiwei Li , Amit Shah , Zhao Liu , Yanan Wang , Helge Deller , Palmer Dabbelt , Ani Sinha , Igor Mammedov , Fabiano Rosas , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Liu Zhiwei , =?utf-8?q?Cl=C3=A9ment_Mathieu--?= =?utf-8?q?Drif?= , qemu-arm@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Huacai Chen , Jason Wang Subject: [PATCH v4 06/27] hw/nvram/fw_cfg: Rename fw_cfg_init_mem_wide() -> fw_cfg_init_mem_dma() Date: Thu, 8 May 2025 15:35:29 +0200 Message-ID: <20250508133550.81391-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250508133550.81391-1-philmd@linaro.org> References: <20250508133550.81391-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "wide" in fw_cfg_init_mem_wide() means "DMA support". Rename for clarity. Suggested-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daudé --- include/hw/nvram/fw_cfg.h | 6 +++--- hw/arm/virt.c | 2 +- hw/nvram/fw_cfg.c | 6 +++--- hw/riscv/virt.c | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index d5161a79436..c4c49886754 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -309,9 +309,9 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, AddressSpace *dma_as); FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, unsigned data_width); -FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, - hwaddr data_addr, uint32_t data_width, - hwaddr dma_addr, AddressSpace *dma_as); +FWCfgState *fw_cfg_init_mem_dma(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as); FWCfgState *fw_cfg_find(void); bool fw_cfg_dma_enabled(void *opaque); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9a6cd085a37..7583f0a85d9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1361,7 +1361,7 @@ static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) FWCfgState *fw_cfg; char *nodename; - fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); + fw_cfg = fw_cfg_init_mem_dma(base + 8, base, 8, base + 16, as); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 4067324fb09..51b028b5d0a 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1087,9 +1087,9 @@ static FWCfgState *fw_cfg_init_mem_internal(hwaddr ctl_addr, return s; } -FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, - hwaddr data_addr, uint32_t data_width, - hwaddr dma_addr, AddressSpace *dma_as) +FWCfgState *fw_cfg_init_mem_dma(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as) { assert(dma_addr && dma_as); return fw_cfg_init_mem_internal(ctl_addr, data_addr, data_addr, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index be1bf0f6468..3ddea18c93e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1266,8 +1266,8 @@ static FWCfgState *create_fw_cfg(const MachineState *ms) hwaddr base = virt_memmap[VIRT_FW_CFG].base; FWCfgState *fw_cfg; - fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, - &address_space_memory); + fw_cfg = fw_cfg_init_mem_dma(base + 8, base, 8, base + 16, + &address_space_memory); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); return fw_cfg;