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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4536366326fsm2312615e9.38.2025.06.19.06.13.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 19 Jun 2025 06:13:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Cameron Esfahani , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Julian Armistead , Radoslaw Biernacki , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Phil Dennis-Jordan , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P?= =?utf-8?q?=2E_Berrang=C3=A9?= , Paolo Bonzini , Peter Maydell , Leif Lindholm , Pierrick Bouvier , Richard Henderson , qemu-arm@nongnu.org, Roman Bolshakov , Alexander Graf Subject: [PATCH 02/20] target/arm: Reduce arm_cpu_post_init() declaration scope Date: Thu, 19 Jun 2025 15:13:01 +0200 Message-ID: <20250619131319.47301-3-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250619131319.47301-1-philmd@linaro.org> References: <20250619131319.47301-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org arm_cpu_post_init() is only used within the same file unit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 -- target/arm/cpu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 302c24e2324..c31f69912b8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1150,8 +1150,6 @@ void arm_gt_sel2vtimer_cb(void *opaque); unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); -void arm_cpu_post_init(Object *obj); - #define ARM_AFF0_SHIFT 0 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) #define ARM_AFF1_SHIFT 8 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e025e241eda..eb0639de719 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1713,7 +1713,7 @@ static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) } } -void arm_cpu_post_init(Object *obj) +static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj);