From patchwork Sat Jun 21 23:50:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 898837 Delivered-To: patch@linaro.org Received: by 2002:adf:e506:0:b0:3a6:d909:26ce with SMTP id j6csp316340wrm; Sat, 21 Jun 2025 16:58:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXV/dlP/0whYlVp4QBvjWIJ2pezg6pHTMqoySd/fVCoElF6G7HGO/U0Nhk5tq6oEPwG+MhWaw==@linaro.org X-Google-Smtp-Source: AGHT+IEBiKv6zOHiO0tU/wMMLRJllv6aC7eJe3baU/CKhpk9+Q+Reetl5mMP336Ftps2pTOZhXpf X-Received: by 2002:a05:622a:c8:b0:4a7:817e:c345 with SMTP id d75a77b69052e-4a78707d14cmr64163001cf.24.1750550323803; Sat, 21 Jun 2025 16:58:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1750550323; cv=none; d=google.com; s=arc-20240605; b=k8JOgXBkdtFw08yEm/acjPFx2pQpJa9ydG7DFAPwUAjt0P9L4+EILWfqPCjxjg9HTS e+k8Jr3Lb7VNIMEyLiSIB2UQ6CCY56jW9IiNbYky4vYaTi70rabtT1eae4vD4/mxwnKQ j2sNsDLQ7A5IjEdsG3F2ejVFkK0BQRd4wr0Dx74plPKItcy1pQy+U85dmJCQTJB3Pc/S n9zpYmL9X/2R9MIHk3GzDJtd1fEdcdTGKLaT9UDcqfnExt6PnFczrPg6CNBReHkA8Ym1 84ebl1OQWQF7RXOkDiVElEGMNklGPfedwjyOmmgIrM7At165l8eN/fUtwQaGLRaH2kVf 6fVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iK5l92DV0hldwJwu9EwpC3QRZ5y+C0O71jPdT0q2JeA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=D0jPhkotafS5s91ssute0NN3pbVwI1j6Rmyf3pYROLt6/2Q6t7IkeCOT2olFHy+IS0 BqP48k00dQOmNFe6X6KyScWmqHb+ckYK1wRwS7VrMvHebn9vouaOGw8pppkHshoxassC CZj5gsi96xEOfadDfq/nmAPBL7UEmbXg+f7Num+PpkG2vBtYxVAce2nFDWuF3l7Pe3ag kv3yEBpX/0k69toBpIc4GhmiyBjyeWQTo83OL1mkHlOsc+MzA75FnoAVXQd60tMfm9Dq gLw2kV2VHeR05ALu59nXG4WqzO6oelG6DiFyPkkcqNzq8dUYbh268VSDDvLRPA8976LB xVTw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gsvX0Hu4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7d3f99e66fbsi479624185a.225.2025.06.21.16.58.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 21 Jun 2025 16:58:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gsvX0Hu4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uT82t-0003tS-4X; Sat, 21 Jun 2025 19:54:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uT82b-000384-Vp for qemu-devel@nongnu.org; Sat, 21 Jun 2025 19:54:34 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uT82W-0005DZ-TA for qemu-devel@nongnu.org; Sat, 21 Jun 2025 19:54:33 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-747fba9f962so2273509b3a.0 for ; Sat, 21 Jun 2025 16:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750550067; x=1751154867; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=iK5l92DV0hldwJwu9EwpC3QRZ5y+C0O71jPdT0q2JeA=; b=gsvX0Hu43D7IXOajASHFjZJLg6WtPZBmkcJgpNRvzIKCMUZsY69ab+adkz3rsgvElz xTPnC0sC329foobKnr0knWLAZECcRT/6mWPY8mXXiiD40cD1xI4DAdSHbToHIoEUrlOP 5JNnvYnVcjh9Df1TjFX9Jbsq6rj3aWBm/7sOGbsJk6+Ny1fWozQxxRih6lv45XasI3Ar GDIwkh3qCwe4XVwaNn0TgRyU9XkfmXDwbbvlDD8KScbHAR7apub84GGhkkJuRfu0E4yw hxhXDK3AoCG5PICvUPMljpH04tZb0vYKeWy6LtkdD/7Bn1NvmRMIfNXc+HsznlpMTn0F B6OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750550067; x=1751154867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iK5l92DV0hldwJwu9EwpC3QRZ5y+C0O71jPdT0q2JeA=; b=cHhpsThRmWnjYf1MeA2cFvSPA5sCVPHn1U8x1sOgYiDpNrXPTeIAEX0ihsU4iAO2vh ivPoDBr76QkM8T9/vp6/WYY5QXQvE/HHvBsS5Eq9ZqapwQNN4ZD7MgZL/xIFggzsWWVq KnLgQyAW6dQl7BkRazGC6LsWzEgBNJVTE5TYBP6H0yo97T22DIrKEpQYDqd0uirxdFCT ul0b4wBH0JtR5CO1B041LuSBr6loKi0VNu2lxJNuBcKNCYZQFekNJaOfmbj35gEVI92D NEc7urP8yxZlU2e3z/1Y8stlhY0hVvLpwkd1RYi5o3X3UEbCPJQ3z5JJu7zZIf9Z67Rp bTKA== X-Gm-Message-State: AOJu0YxY9R6VHjEgMEdzCJxFg2GZV6mKNdMXQpyxt7LtLEy2fz/a4h4F roTgVKMUEMqvkAiM/2hsPR5QcnFug0JafUTAGtiQJZfgK1yxvTjhBQQK0XC+zc5tjP+7AFT00KY rMK1GWIo= X-Gm-Gg: ASbGncsKNqK2sgVlqIvPNvtBFIOmRlXn7g6BnjO0tTMKWBImPAq/3bwMNo3Es6t3iAu 4nWhPqv1hcNd0sslYMtukm7PDDaxwFPqeotEVs9VddwP+R38Vd/hlM1lrz+fwuIU+ljgNmZ/Am8 2Y1d44WMEjs4JvXB6mQOGCIS/2heD4XGNOl3mHegMca9xnTB+Pdm+sN0xq0ksqWbxEn0CwP79oU pz+WvHfJxRJ2gkPPUwwVFYUATUfuSdp7gh4RoBGPuIlPaxGWMKLEuVg1XK4AIgkFgLYzzUOoBC+ XB8Ig5Dd+G6LXMVNXaR8R64+lzC1d+hCL+FEq2s5ocC/kFTb9p5h49LJyNPCmDF+SitAmAAv7ND Cl7NC5pWPa5J1kNBHHUAK+k6gnu9kI4U= X-Received: by 2002:a05:6a00:8783:b0:746:1c67:f6cb with SMTP id d2e1a72fcca58-7490f4bebdbmr8627578b3a.5.1750550067340; Sat, 21 Jun 2025 16:54:27 -0700 (PDT) Received: from stoup.. (174-21-67-243.tukw.qwest.net. [174.21.67.243]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7490a46b590sm4970051b3a.27.2025.06.21.16.54.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Jun 2025 16:54:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 076/101] target/arm: Implement SVE2p1 WHILE (predicate pair) Date: Sat, 21 Jun 2025 16:50:12 -0700 Message-ID: <20250621235037.74091-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250621235037.74091-1-richard.henderson@linaro.org> References: <20250621235037.74091-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sve.h | 3 +++ target/arm/tcg/sve_helper.c | 44 ++++++++++++++++++++++++++++++++++ target/arm/tcg/translate-sve.c | 14 +++++++---- target/arm/tcg/sve.decode | 8 +++++++ 4 files changed, 65 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h index 0b1b588783..eac23e75b9 100644 --- a/target/arm/tcg/helper-sve.h +++ b/target/arm/tcg/helper-sve.h @@ -941,6 +941,9 @@ DEF_HELPER_FLAGS_3(sve_cntp, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_whilel, TCG_CALL_NO_RWG, i32, ptr, i32, i32) DEF_HELPER_FLAGS_3(sve_whileg, TCG_CALL_NO_RWG, i32, ptr, i32, i32) +DEF_HELPER_FLAGS_3(sve_while2l, TCG_CALL_NO_RWG, i32, ptr, i32, i32) +DEF_HELPER_FLAGS_3(sve_while2g, TCG_CALL_NO_RWG, i32, ptr, i32, i32) + DEF_HELPER_FLAGS_4(sve_subri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(sve_subri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(sve_subri_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index dbb88e9a39..2beb012292 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -4157,6 +4157,28 @@ uint32_t HELPER(sve_whilel)(void *vd, uint32_t count, uint32_t pred_desc) return pred_count_test(oprbits, count, false); } +uint32_t HELPER(sve_while2l)(void *vd, uint32_t count, uint32_t pred_desc) +{ + uint32_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + uint32_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ); + uint32_t oprbits = oprsz * 8; + uint64_t esz_mask = pred_esz_masks[esz]; + ARMPredicateReg *d = vd; + + do_zero(&d[0], oprsz); + do_zero(&d[1], oprsz); + + count <<= esz; + if (count <= oprbits) { + do_whilel(d[0].p, esz_mask, count, oprbits); + } else { + do_whilel(d[0].p, esz_mask, oprbits, oprbits); + do_whilel(d[1].p, esz_mask, count - oprbits, oprbits); + } + + return pred_count_test(2 * oprbits, count, false); +} + static void do_whileg(uint64_t *d, uint64_t esz_mask, uint32_t count, uint32_t oprbits) { @@ -4190,6 +4212,28 @@ uint32_t HELPER(sve_whileg)(void *vd, uint32_t count, uint32_t pred_desc) return pred_count_test(oprbits, count, true); } +uint32_t HELPER(sve_while2g)(void *vd, uint32_t count, uint32_t pred_desc) +{ + uint32_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + uint32_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ); + uint32_t oprbits = oprsz * 8; + uint64_t esz_mask = pred_esz_masks[esz]; + ARMPredicateReg *d = vd; + + do_zero(&d[0], oprsz); + do_zero(&d[1], oprsz); + + count <<= esz; + if (count <= oprbits) { + do_whileg(d[0].p, esz_mask, count, oprbits); + } else { + do_whileg(d[0].p, esz_mask, oprbits, oprbits); + do_whileg(d[1].p, esz_mask, count - oprbits, oprbits); + } + + return pred_count_test(2 * oprbits, count, true); +} + /* Recursive reduction on a function; * C.f. the ARM ARM function ReducePredicated. * diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 9a6fa8ee8a..c2a5b2f76f 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3092,7 +3092,8 @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a) } typedef void gen_while_fn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); -static bool do_WHILE(DisasContext *s, arg_while *a, bool lt, gen_while_fn *fn) +static bool do_WHILE(DisasContext *s, arg_while *a, + bool lt, int scale, gen_while_fn *fn) { TCGv_i64 op0, op1, t0, t1, tmax; TCGv_i32 t2; @@ -3147,7 +3148,7 @@ static bool do_WHILE(DisasContext *s, arg_while *a, bool lt, gen_while_fn *fn) } } - tmax = tcg_constant_i64(vsz >> a->esz); + tmax = tcg_constant_i64((vsz << scale) >> a->esz); if (eq) { /* Equality means one more iteration. */ tcg_gen_addi_i64(t0, t0, 1); @@ -3188,8 +3189,13 @@ static bool do_WHILE(DisasContext *s, arg_while *a, bool lt, gen_while_fn *fn) return true; } -TRANS_FEAT(WHILE_lt, aa64_sve, do_WHILE, a, true, gen_helper_sve_whilel) -TRANS_FEAT(WHILE_gt, aa64_sve2, do_WHILE, a, false, gen_helper_sve_whileg) +TRANS_FEAT(WHILE_lt, aa64_sve, do_WHILE, a, true, 0, gen_helper_sve_whilel) +TRANS_FEAT(WHILE_gt, aa64_sve2, do_WHILE, a, false, 0, gen_helper_sve_whileg) + +TRANS_FEAT(WHILE_lt_pair, aa64_sme2_or_sve2p1, do_WHILE, + a, true, 1, gen_helper_sve_while2l) +TRANS_FEAT(WHILE_gt_pair, aa64_sme2_or_sve2p1, do_WHILE, + a, false, 1, gen_helper_sve_while2g) static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) { diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 525c11f5d4..a919fe117b 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -796,6 +796,14 @@ WHILE_gt 00100101 esz:2 1 rm:5 000 sf:1 u:1 0 rn:5 eq:1 rd:4 &while # SVE2 pointer conflict compare WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4 +# SVE2.1 predicate pair +%pd_pair 1:3 !function=times_2 +@while_pair ........ esz:2 . rm:5 .... u:1 . rn:5 . ... eq:1 \ + &while rd=%pd_pair sf=1 + +WHILE_lt_pair 00100101 .. 1 ..... 0101 . 1 ..... 1 ... . @while_pair +WHILE_gt_pair 00100101 .. 1 ..... 0101 . 0 ..... 1 ... . @while_pair + ### SVE Integer Wide Immediate - Unpredicated Group # SVE broadcast floating-point immediate (unpredicated)